tree a00f7f5abcb66194266de22675c3bd5ec003be7f
parent 3723cda9c2baa704602acaa8f941a996a636df49
author Adrian Herrera <adrian.herrera@arm.com> 1573047015 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1576660448 +0000

arch-arm: AArch64 trap check, arbitrary ECs/Imms

This patch generalises trap checking when accessing system registers
in AArch64. Depending on the accessed register, a different Exception
Class (EC) and immediate value may be set.
Previously this only took SIMD traps into account.

Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>