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#ifndef __ARCH_ARM_FASTMODEL_RESET_CONTROLLER_EXAMPLE_HH__
#define __ARCH_ARM_FASTMODEL_RESET_CONTROLLER_EXAMPLE_HH__

#include <string>

#include "arch/arm/fastmodel/iris/cpu.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/reg_bank.hh"
#include "mem/packet_access.hh"
#include "params/FastModelResetControllerExample.hh"

namespace gem5
{

namespace fastmodel
{

class ResetControllerExample : public BasicPioDevice
{
  private:
    struct CorePins
    {
        using CoreInt = IntSourcePin<CorePins>;
        CoreInt reset;
        CoreInt halt;

        explicit CorePins(const std::string &);
    };

    class Registers : public RegisterBankLE
    {
      private:
        Iris::BaseCPU *cpu;
        CorePins *pins;

        Register64 nsrvbar;
        Register64 rvbar;
        Register32 reset;
        Register32 halt;

      public:
        Registers(const std::string &, Iris::BaseCPU *, CorePins *);
    };

    CorePins pins;
    Registers registers;

  public:
    using Params = FastModelResetControllerExampleParams;
    explicit ResetControllerExample(const Params &);

    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
    Port &getPort(const std::string &, PortID = InvalidPortID) override;
};

} // namespace fastmodel
} // namespace gem5

#endif  // __ARCH_ARM_FASTMODEL_RESET_CONTROLLER_EXAMPLE_HH__