| commit | ba8f59ff1718883ba2624a52fe50d8cff8aff328 | [log] [tgz] |
|---|---|---|
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | Mon Oct 31 13:58:14 2022 +0000 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Wed Nov 02 08:32:44 2022 +0000 |
| tree | 36dd52ae2596d09298175ad8d6d00839b0070ccb | |
| parent | e65adccd6f4c89478d19ed23c22111a934ad35fe [diff] |
arch-arm: Fix access permissions for GICv3 cpu registers * ICC_SRE_EL3/ICC_CTLR_EL3/MISCREG_ICC_IGRPEN1_EL3 are accessible at EL3 only * ICH_LR<n>_EL2 are accessible at EL2 and EL3 only Change-Id: Idcd9656abafc3014d2715cd6f138a6d786bc6c34 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65171 Tested-by: kokoro <noreply+kokoro@google.com>