tree 85df4b0b793ccd2fae0a3c5b73862e373d5e3fce
parent f019d9f866cb5bfd639365c13f325d128f745f7f
author Sandipan Das <sandipan@linux.ibm.com> 1612614067 +0530
committer Boris Shingarov <shingarov@labware.com> 1625422815 +0000

arch-power: Fix load-store timing sequence

To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.

The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
  * Load Byte and Zero with Update (lbzu)
  * Load Halfword and Zero with Update (lhzu)
  * Load Halfword Algebraic with Update (lhau)
  * Load Word and Zero with Update (lwzu)
  * Load Doubleword with Update (ldu)
  * Load Floating Single with Update (lfsu)
  * Load Floating Double with Update (lfdu)
  * Load Byte and Zero with Update Indexed (lbzux)
  * Load Halfword and Zero with Update Indexed (lhzux)
  * Load Halfword Algebraic with Update Indexed (lhaux)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word Algebraic with Update Indexed (lwaux)
  * Load Doubleword with Update Indexed (ldux)
  * Load Floating Single with Update Indexed (lfsux)
  * Load Floating Double with Update Indexed (lfdux)
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Word And Reserve Indexed (lwarx)
  * Load Doubleword And Reserve Indexed (ldarx)
  * Store Byte with Update (stbu)
  * Store Halfword with Update (sthu)
  * Store Word with Update (stwu)
  * Store Doubleword with Update (stdu)
  * Store Byte with Update Indexed (stbux)
  * Store Halfword with Update Indexed (sthux)
  * Store Word with Update Indexed (stwux)
  * Store Doubleword with Update Indexed (stdux)
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Word Conditional Indexed (stwcx.)
  * Store Doubleword Conditional Indexed (stdcx.)
  * Store Floating Single with Update (stfsu)
  * Store Floating Double with Update (stdsu)
  * Store Floating Single with Update Indexed (stfsux)
  * Store Floating Double with Update Indexed (stfdux)

Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40947
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>