diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh
index 0e842bd..64b7ea7 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.hh
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh
@@ -37,7 +37,7 @@
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
-#include "mem/protocol/InvalidateGeneratorStatus.hh"
+#include "mem/ruby/protocol/InvalidateGeneratorStatus.hh"
 #include "params/InvalidateGenerator.hh"
 
 class InvalidateGenerator : public DirectedGenerator
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 8c64a3d..77688b6 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -37,7 +37,7 @@
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
-#include "mem/protocol/SeriesRequestGeneratorStatus.hh"
+#include "mem/ruby/protocol/SeriesRequestGeneratorStatus.hh"
 #include "params/SeriesRequestGenerator.hh"
 
 class SeriesRequestGenerator : public DirectedGenerator
diff --git a/src/cpu/testers/rubytest/Check.hh b/src/cpu/testers/rubytest/Check.hh
index f7922d7..1a33174 100644
--- a/src/cpu/testers/rubytest/Check.hh
+++ b/src/cpu/testers/rubytest/Check.hh
@@ -33,9 +33,9 @@
 #include <iostream>
 
 #include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/TesterStatus.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/TesterStatus.hh"
 
 class SubBlock;
 
diff --git a/src/learning_gem5/part3/MSI-cache.sm b/src/learning_gem5/part3/MSI-cache.sm
index 3847b53..0d5a205 100644
--- a/src/learning_gem5/part3/MSI-cache.sm
+++ b/src/learning_gem5/part3/MSI-cache.sm
@@ -482,7 +482,7 @@
             // across different directories, so query the network.
             out_msg.Destination.add(mapAddressToMachine(address,
                                     MachineType:Directory));
-            // See mem/protocol/RubySlicc_Exports.sm for possible sizes.
+            // See mem/ruby/protocol/RubySlicc_Exports.sm for possible sizes.
             out_msg.MessageSize := MessageSizeType:Control;
             // Set that the reqeustor is this machine so we get the response.
             out_msg.Requestor := machineID;
diff --git a/src/learning_gem5/part3/SConsopts b/src/learning_gem5/part3/SConsopts
index c8573d3..6525d4e 100644
--- a/src/learning_gem5/part3/SConsopts
+++ b/src/learning_gem5/part3/SConsopts
@@ -1,6 +1,6 @@
 Import('*')
 
-# NOTE: All SLICC setup code found in src/mem/protocol/SConscript
+# NOTE: All SLICC setup code found in src/mem/ruby/protocol/SConscript
 
 # Register this protocol with gem5/SCons
 all_protocols.extend([
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index be52c02..22dd973 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -98,7 +98,7 @@
 #
 # Link includes
 #
-generated_dir = Dir('../protocol')
+generated_dir = Dir('protocol')
 
 def MakeIncludeAction(target, source, env):
     f = file(str(target[0]), 'w')
@@ -138,9 +138,9 @@
 MakeInclude('system/DMASequencer.hh')
 MakeInclude('system/Sequencer.hh')
 
-# External types : Group "mem/protocol" : include "header.hh" to the bottom
-# of this MakeIncludes if it is referenced as
-# <# include "mem/protocol/header.hh"> in any file
-# generated_dir = Dir('../protocol')
+# External types : Group "mem/ruby/protocol" : include "header.hh" to the
+# bottom of this MakeIncludes if it is referenced as
+# <# include "mem/ruby/protocol/header.hh"> in any file
+# generated_dir = Dir('protocol')
 MakeInclude('system/GPUCoalescer.hh')
 MakeInclude('system/VIPERCoalescer.hh')
diff --git a/src/mem/ruby/common/MachineID.hh b/src/mem/ruby/common/MachineID.hh
index 8fe8f80..64082d7 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -33,7 +33,7 @@
 #include <string>
 
 #include "base/cprintf.hh"
-#include "mem/protocol/MachineType.hh"
+#include "mem/ruby/protocol/MachineType.hh"
 
 struct MachineID
 {
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 0830187..606e670 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -61,12 +61,12 @@
 #include "base/types.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
-#include "mem/protocol/LinkDirection.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/Topology.hh"
 #include "mem/ruby/network/dummy_port.hh"
+#include "mem/ruby/protocol/LinkDirection.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 #include "params/RubyNetwork.hh"
 #include "sim/clocked_object.hh"
 
diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh
index 71faf41..ef8104a 100644
--- a/src/mem/ruby/network/Topology.hh
+++ b/src/mem/ruby/network/Topology.hh
@@ -44,9 +44,9 @@
 #include <string>
 #include <vector>
 
-#include "mem/protocol/LinkDirection.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/protocol/LinkDirection.hh"
 
 class NetDest;
 class Network;
diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh
index dbb1bbd..b481ed5 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -43,9 +43,9 @@
 #include <vector>
 
 #include "mem/packet.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/BasicRouter.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 #include "params/Switch.hh"
 
 class MessageBuffer;
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index 3e9d544..0d6f71e 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -31,10 +31,10 @@
 
 #include <iostream>
 
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Set.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class Histogram;
 
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 087b774..acdc860 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -31,8 +31,8 @@
 #include <vector>
 
 #include "base/stl_helpers.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 using namespace std;
 typedef AddressProfiler::AddressMap AddressMap;
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 9f12415..14d015c 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -32,12 +32,12 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/AccessType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Histogram.hh"
 #include "mem/ruby/profiler/AccessTraceForAddress.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/AccessType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 class Set;
 
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 900714e..505e3a1 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -52,10 +52,10 @@
 
 #include "base/stl_helpers.hh"
 #include "base/str.hh"
-#include "mem/protocol/MachineType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/profiler/AddressProfiler.hh"
+#include "mem/ruby/protocol/MachineType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 
 /**
  * the profiler uses GPUCoalescer code even
@@ -72,6 +72,7 @@
  */
 #ifdef BUILD_GPU
 #include "mem/ruby/system/GPUCoalescer.hh"
+
 #endif
 
 #include "mem/ruby/system/Sequencer.hh"
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 6ad65f9..5632b84 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -51,11 +51,11 @@
 
 #include "base/callback.hh"
 #include "base/statistics.hh"
-#include "mem/protocol/AccessType.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/MachineID.hh"
+#include "mem/ruby/protocol/AccessType.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 #include "params/RubySystem.hh"
 
 class RubyRequest;
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/ruby/protocol/GPU_RfO-SQC.sm
similarity index 100%
rename from src/mem/protocol/GPU_RfO-SQC.sm
rename to src/mem/ruby/protocol/GPU_RfO-SQC.sm
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/ruby/protocol/GPU_RfO-TCC.sm
similarity index 100%
rename from src/mem/protocol/GPU_RfO-TCC.sm
rename to src/mem/ruby/protocol/GPU_RfO-TCC.sm
diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
similarity index 100%
rename from src/mem/protocol/GPU_RfO-TCCdir.sm
rename to src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/ruby/protocol/GPU_RfO-TCP.sm
similarity index 100%
rename from src/mem/protocol/GPU_RfO-TCP.sm
rename to src/mem/ruby/protocol/GPU_RfO-TCP.sm
diff --git a/src/mem/protocol/GPU_RfO.slicc b/src/mem/ruby/protocol/GPU_RfO.slicc
similarity index 100%
rename from src/mem/protocol/GPU_RfO.slicc
rename to src/mem/ruby/protocol/GPU_RfO.slicc
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
similarity index 100%
rename from src/mem/protocol/GPU_VIPER-SQC.sm
rename to src/mem/ruby/protocol/GPU_VIPER-SQC.sm
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
similarity index 100%
rename from src/mem/protocol/GPU_VIPER-TCC.sm
rename to src/mem/ruby/protocol/GPU_VIPER-TCC.sm
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
similarity index 100%
rename from src/mem/protocol/GPU_VIPER-TCP.sm
rename to src/mem/ruby/protocol/GPU_VIPER-TCP.sm
diff --git a/src/mem/protocol/GPU_VIPER.slicc b/src/mem/ruby/protocol/GPU_VIPER.slicc
similarity index 100%
rename from src/mem/protocol/GPU_VIPER.slicc
rename to src/mem/ruby/protocol/GPU_VIPER.slicc
diff --git a/src/mem/protocol/GPU_VIPER_Baseline.slicc b/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
similarity index 100%
rename from src/mem/protocol/GPU_VIPER_Baseline.slicc
rename to src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
similarity index 100%
rename from src/mem/protocol/GPU_VIPER_Region-TCC.sm
rename to src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
diff --git a/src/mem/protocol/GPU_VIPER_Region.slicc b/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
similarity index 100%
rename from src/mem/protocol/GPU_VIPER_Region.slicc
rename to src/mem/ruby/protocol/GPU_VIPER_Region.slicc
diff --git a/src/mem/protocol/Garnet_standalone-cache.sm b/src/mem/ruby/protocol/Garnet_standalone-cache.sm
similarity index 100%
rename from src/mem/protocol/Garnet_standalone-cache.sm
rename to src/mem/ruby/protocol/Garnet_standalone-cache.sm
diff --git a/src/mem/protocol/Garnet_standalone-dir.sm b/src/mem/ruby/protocol/Garnet_standalone-dir.sm
similarity index 100%
rename from src/mem/protocol/Garnet_standalone-dir.sm
rename to src/mem/ruby/protocol/Garnet_standalone-dir.sm
diff --git a/src/mem/protocol/Garnet_standalone-msg.sm b/src/mem/ruby/protocol/Garnet_standalone-msg.sm
similarity index 100%
rename from src/mem/protocol/Garnet_standalone-msg.sm
rename to src/mem/ruby/protocol/Garnet_standalone-msg.sm
diff --git a/src/mem/protocol/Garnet_standalone.slicc b/src/mem/ruby/protocol/Garnet_standalone.slicc
similarity index 100%
rename from src/mem/protocol/Garnet_standalone.slicc
rename to src/mem/ruby/protocol/Garnet_standalone.slicc
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
similarity index 100%
rename from src/mem/protocol/MESI_Three_Level-L0cache.sm
rename to src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
similarity index 100%
rename from src/mem/protocol/MESI_Three_Level-L1cache.sm
rename to src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
similarity index 100%
rename from src/mem/protocol/MESI_Three_Level-msg.sm
rename to src/mem/ruby/protocol/MESI_Three_Level-msg.sm
diff --git a/src/mem/protocol/MESI_Three_Level.slicc b/src/mem/ruby/protocol/MESI_Three_Level.slicc
similarity index 100%
rename from src/mem/protocol/MESI_Three_Level.slicc
rename to src/mem/ruby/protocol/MESI_Three_Level.slicc
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level-L1cache.sm
rename to src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level-L2cache.sm
rename to src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level-dir.sm
rename to src/mem/ruby/protocol/MESI_Two_Level-dir.sm
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level-dma.sm
rename to src/mem/ruby/protocol/MESI_Two_Level-dma.sm
diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level-msg.sm
rename to src/mem/ruby/protocol/MESI_Two_Level-msg.sm
diff --git a/src/mem/protocol/MESI_Two_Level.slicc b/src/mem/ruby/protocol/MESI_Two_Level.slicc
similarity index 100%
rename from src/mem/protocol/MESI_Two_Level.slicc
rename to src/mem/ruby/protocol/MESI_Two_Level.slicc
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/ruby/protocol/MI_example-cache.sm
similarity index 100%
rename from src/mem/protocol/MI_example-cache.sm
rename to src/mem/ruby/protocol/MI_example-cache.sm
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/ruby/protocol/MI_example-dir.sm
similarity index 100%
rename from src/mem/protocol/MI_example-dir.sm
rename to src/mem/ruby/protocol/MI_example-dir.sm
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/ruby/protocol/MI_example-dma.sm
similarity index 100%
rename from src/mem/protocol/MI_example-dma.sm
rename to src/mem/ruby/protocol/MI_example-dma.sm
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/ruby/protocol/MI_example-msg.sm
similarity index 100%
rename from src/mem/protocol/MI_example-msg.sm
rename to src/mem/ruby/protocol/MI_example-msg.sm
diff --git a/src/mem/protocol/MI_example.slicc b/src/mem/ruby/protocol/MI_example.slicc
similarity index 100%
rename from src/mem/protocol/MI_example.slicc
rename to src/mem/ruby/protocol/MI_example.slicc
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-CorePair.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-L3cache.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-dir.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-msg.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-msg.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
rename to src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
diff --git a/src/mem/protocol/MOESI_AMD_Base.slicc b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
similarity index 100%
rename from src/mem/protocol/MOESI_AMD_Base.slicc
rename to src/mem/ruby/protocol/MOESI_AMD_Base.slicc
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory-L1cache.sm
rename to src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory-L2cache.sm
rename to src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory-dir.sm
rename to src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory-dma.sm
rename to src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory-msg.sm
rename to src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
diff --git a/src/mem/protocol/MOESI_CMP_directory.slicc b/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_directory.slicc
rename to src/mem/ruby/protocol/MOESI_CMP_directory.slicc
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token-L1cache.sm
rename to src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token-L2cache.sm
rename to src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token-dir.sm
rename to src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token-dma.sm
rename to src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token-msg.sm
rename to src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
diff --git a/src/mem/protocol/MOESI_CMP_token.slicc b/src/mem/ruby/protocol/MOESI_CMP_token.slicc
similarity index 100%
rename from src/mem/protocol/MOESI_CMP_token.slicc
rename to src/mem/ruby/protocol/MOESI_CMP_token.slicc
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
similarity index 100%
rename from src/mem/protocol/MOESI_hammer-cache.sm
rename to src/mem/ruby/protocol/MOESI_hammer-cache.sm
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
similarity index 100%
rename from src/mem/protocol/MOESI_hammer-dir.sm
rename to src/mem/ruby/protocol/MOESI_hammer-dir.sm
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/ruby/protocol/MOESI_hammer-dma.sm
similarity index 100%
rename from src/mem/protocol/MOESI_hammer-dma.sm
rename to src/mem/ruby/protocol/MOESI_hammer-dma.sm
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/ruby/protocol/MOESI_hammer-msg.sm
similarity index 100%
rename from src/mem/protocol/MOESI_hammer-msg.sm
rename to src/mem/ruby/protocol/MOESI_hammer-msg.sm
diff --git a/src/mem/protocol/MOESI_hammer.slicc b/src/mem/ruby/protocol/MOESI_hammer.slicc
similarity index 100%
rename from src/mem/protocol/MOESI_hammer.slicc
rename to src/mem/ruby/protocol/MOESI_hammer.slicc
diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_ComponentMapping.sm
rename to src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/ruby/protocol/RubySlicc_Defines.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_Defines.sm
rename to src/mem/ruby/protocol/RubySlicc_Defines.sm
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/ruby/protocol/RubySlicc_Exports.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_Exports.sm
rename to src/mem/ruby/protocol/RubySlicc_Exports.sm
diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_MemControl.sm
rename to src/mem/ruby/protocol/RubySlicc_MemControl.sm
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_Types.sm
rename to src/mem/ruby/protocol/RubySlicc_Types.sm
diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/ruby/protocol/RubySlicc_Util.sm
similarity index 100%
rename from src/mem/protocol/RubySlicc_Util.sm
rename to src/mem/ruby/protocol/RubySlicc_Util.sm
diff --git a/src/mem/protocol/RubySlicc_interfaces.slicc b/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
similarity index 100%
rename from src/mem/protocol/RubySlicc_interfaces.slicc
rename to src/mem/ruby/protocol/RubySlicc_interfaces.slicc
diff --git a/src/mem/protocol/SConscript b/src/mem/ruby/protocol/SConscript
similarity index 98%
rename from src/mem/protocol/SConscript
rename to src/mem/ruby/protocol/SConscript
index e66c6b3..e5a6f6d 100644
--- a/src/mem/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -47,7 +47,7 @@
 html_dir = Dir('html')
 slicc_dir = Dir('../slicc')
 
-sys.path[1:1] = [ Dir('..').srcnode().abspath ]
+sys.path[1:1] = [ Dir('..').Dir('..').srcnode().abspath ]
 from slicc.parser import SLICC
 
 slicc_depends = []
diff --git a/src/mem/protocol/SConsopts b/src/mem/ruby/protocol/SConsopts
similarity index 100%
rename from src/mem/protocol/SConsopts
rename to src/mem/ruby/protocol/SConsopts
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index f0e9500..c943c75 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -36,8 +36,8 @@
 #include <iostream>
 
 #include "base/logging.hh"
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 
 class DataBlock;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index c953e82..cc1ac26 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -41,8 +41,8 @@
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 
 #include "debug/RubyQueue.hh"
-#include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/network/Network.hh"
+#include "mem/ruby/protocol/MemoryMsg.hh"
 #include "mem/ruby/system/GPUCoalescer.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/ruby/system/Sequencer.hh"
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 8888bd0..2007026 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -48,7 +48,6 @@
 #include "base/addr_range.hh"
 #include "base/callback.hh"
 #include "mem/packet.hh"
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/qport.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
@@ -56,6 +55,7 @@
 #include "mem/ruby/common/Histogram.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/system/CacheRecorder.hh"
 #include "params/RubyController.hh"
 #include "sim/clocked_object.hh"
diff --git a/src/mem/ruby/slicc_interface/AbstractEntry.hh b/src/mem/ruby/slicc_interface/AbstractEntry.hh
index 2cf1c4b..a75055f 100644
--- a/src/mem/ruby/slicc_interface/AbstractEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractEntry.hh
@@ -31,7 +31,7 @@
 
 #include <iostream>
 
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 
 class AbstractEntry
 {
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
index c62b4e1..0c2e0aa 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -34,8 +34,8 @@
 #include <stack>
 
 #include "mem/packet.hh"
-#include "mem/protocol/MessageSizeType.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/MessageSizeType.hh"
 
 class Message;
 typedef std::shared_ptr<Message> MsgPtr;
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 6c84f38..f6b25bf 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -32,15 +32,15 @@
 #include <ostream>
 #include <vector>
 
-#include "mem/protocol/HSAScope.hh"
-#include "mem/protocol/HSASegment.hh"
-#include "mem/protocol/Message.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/WriteMask.hh"
+#include "mem/ruby/protocol/HSAScope.hh"
+#include "mem/ruby/protocol/HSASegment.hh"
+#include "mem/ruby/protocol/Message.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class RubyRequest : public Message
 {
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index dfc2c73..a48405d 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -29,10 +29,10 @@
 #ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 #define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
 
-#include "mem/protocol/MachineType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/MachineType.hh"
 #include "mem/ruby/structures/DirectoryMemory.hh"
 
 inline NetDest
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 6c93c32..5dc3463 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -35,7 +35,7 @@
 #include "debug/RubyCacheTrace.hh"
 #include "debug/RubyResourceStalls.hh"
 #include "debug/RubyStats.hh"
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/ruby/system/WeightedLRUPolicy.hh"
 
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 5b30505..16339ee 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -35,10 +35,10 @@
 #include <vector>
 
 #include "base/statistics.hh"
-#include "mem/protocol/CacheRequestType.hh"
-#include "mem/protocol/CacheResourceType.hh"
-#include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/DataBlock.hh"
+#include "mem/ruby/protocol/CacheRequestType.hh"
+#include "mem/ruby/protocol/CacheResourceType.hh"
+#include "mem/ruby/protocol/RubyRequest.hh"
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/structures/AbstractReplacementPolicy.hh"
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh b/src/mem/ruby/structures/DirectoryMemory.hh
index 36defd5..bbed4f9 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -45,8 +45,8 @@
 #include <string>
 
 #include "base/addr_range.hh"
-#include "mem/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 #include "params/RubyDirectoryMemory.hh"
 #include "sim/sim_object.hh"
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 61d5e12..363e3e8 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -31,8 +31,8 @@
 
 #include <unordered_map>
 
-#include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 
 template<class ENTRY>
 struct PerfectCacheLineState
diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh
index e5296d1..bc1d79e 100644
--- a/src/mem/ruby/structures/PersistentTable.hh
+++ b/src/mem/ruby/structures/PersistentTable.hh
@@ -32,10 +32,10 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/AccessType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/NetDest.hh"
+#include "mem/ruby/protocol/AccessType.hh"
 
 class PersistentTableEntry
 {
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index 7748b4c..53ab8e5 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -38,10 +38,10 @@
 #include <vector>
 
 #include "base/types.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/common/TypeDefines.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 
 class Sequencer;
 
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 0ad8a20..bad49c9 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -32,8 +32,8 @@
 
 #include "debug/RubyDma.hh"
 #include "debug/RubyStats.hh"
-#include "mem/protocol/SequencerMsg.hh"
-#include "mem/protocol/SequencerRequestType.hh"
+#include "mem/ruby/protocol/SequencerMsg.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 9f1f4e5..a3ee8af 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -33,9 +33,9 @@
 #include <ostream>
 #include <unordered_map>
 
-#include "mem/protocol/DMASequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/DataBlock.hh"
+#include "mem/ruby/protocol/DMASequencerRequestType.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "params/DMASequencer.hh"
 
diff --git a/src/mem/ruby/system/GPUCoalescer.hh b/src/mem/ruby/system/GPUCoalescer.hh
index 6e40238..56f81c6 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -40,15 +40,15 @@
 #include <unordered_map>
 
 #include "base/statistics.hh"
-#include "mem/protocol/HSAScope.hh"
-#include "mem/protocol/HSASegment.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
-#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/request.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/HSAScope.hh"
+#include "mem/ruby/protocol/HSASegment.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/system/Sequencer.hh"
 
 class DataBlock;
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ff3bbe8..800046e 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -45,7 +45,7 @@
 #include "debug/Config.hh"
 #include "debug/Drain.hh"
 #include "debug/Ruby.hh"
-#include "mem/protocol/AccessPermission.hh"
+#include "mem/ruby/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/simple_mem.hh"
 #include "sim/full_system.hh"
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 20bc03a..b57828d 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -45,9 +45,9 @@
 #include <cassert>
 #include <string>
 
-#include "mem/protocol/RequestStatus.hh"
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
+#include "mem/ruby/protocol/RequestStatus.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "mem/tport.hh"
 #include "params/RubyPort.hh"
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index ba67311..9d317aa 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -37,9 +37,9 @@
 #include "debug/RubySequencer.hh"
 #include "debug/RubyStats.hh"
 #include "mem/packet.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
 #include "mem/ruby/slicc_interface/RubyRequest.hh"
 #include "mem/ruby/system/RubySystem.hh"
 #include "sim/system.hh"
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index fcfa8ad..33fd530 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -32,10 +32,10 @@
 #include <iostream>
 #include <unordered_map>
 
-#include "mem/protocol/MachineType.hh"
-#include "mem/protocol/RubyRequestType.hh"
-#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
+#include "mem/ruby/protocol/MachineType.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
+#include "mem/ruby/protocol/SequencerRequestType.hh"
 #include "mem/ruby/structures/CacheMemory.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "params/RubySequencer.hh"
diff --git a/src/mem/ruby/system/VIPERCoalescer.hh b/src/mem/ruby/system/VIPERCoalescer.hh
index 0727ea7..3f35978 100644
--- a/src/mem/ruby/system/VIPERCoalescer.hh
+++ b/src/mem/ruby/system/VIPERCoalescer.hh
@@ -38,11 +38,11 @@
 
 #include <iostream>
 
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/PrefetchBit.hh"
+#include "mem/ruby/protocol/RubyAccessMode.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
 #include "mem/ruby/system/GPUCoalescer.hh"
 #include "mem/ruby/system/RubyPort.hh"
 
diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py
index f2a4751..f7f0494 100644
--- a/src/mem/slicc/main.py
+++ b/src/mem/slicc/main.py
@@ -90,7 +90,8 @@
     output("SLICC v0.4")
     output("Parsing...")
 
-    protocol_base = os.path.join(os.path.dirname(__file__), '..', 'protocol')
+    protocol_base = os.path.join(os.path.dirname(__file__),
+                                 '..', 'ruby', 'protocol')
     slicc = SLICC(slicc_file, protocol_base, verbose=True, debug=opts.debug,
                   traceback=opts.tb)
 
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 03e624b..a92e078 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -230,7 +230,7 @@
 
 class $py_ident(RubyController):
     type = '$py_ident'
-    cxx_header = 'mem/protocol/${c_ident}.hh'
+    cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
 ''')
         code.indent()
         for param in self.config_parameters:
@@ -272,9 +272,9 @@
 #include <sstream>
 #include <string>
 
-#include "mem/protocol/TransitionResult.hh"
-#include "mem/protocol/Types.hh"
 #include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/protocol/TransitionResult.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "params/$c_ident.hh"
 
@@ -283,7 +283,7 @@
         seen_types = set()
         for var in self.objects:
             if var.type.ident not in seen_types and not var.type.isPrimitive:
-                code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{var.type.c_ident}}.hh"')
                 seen_types.add(var.type.ident)
 
         # for adding information to the protocol debug trace
@@ -459,18 +459,18 @@
 #include <typeinfo>
 
 #include "base/compiler.hh"
-#include "mem/ruby/common/BoolVec.hh"
 #include "base/cprintf.hh"
+#include "mem/ruby/common/BoolVec.hh"
 
 ''')
         for f in self.debug_flags:
             code('#include "debug/${{f}}.hh"')
         code('''
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
-#include "mem/protocol/Types.hh"
 #include "mem/ruby/network/Network.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 ''')
@@ -486,7 +486,7 @@
         seen_types = set()
         for var in self.objects:
             if var.type.ident not in seen_types and not var.type.isPrimitive:
-                code('#include "mem/protocol/${{var.type.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{var.type.c_ident}}.hh"')
             seen_types.add(var.type.ident)
 
         num_in_ports = len(self.in_ports)
@@ -1057,17 +1057,17 @@
         for f in self.debug_flags:
             code('#include "debug/${{f}}.hh"')
         code('''
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
 
 ''')
 
         if outputRequest_types:
-            code('''#include "mem/protocol/${ident}_RequestType.hh"''')
+            code('''#include "mem/ruby/protocol/${ident}_RequestType.hh"''')
 
         code('''
-#include "mem/protocol/Types.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 ''')
@@ -1172,10 +1172,10 @@
 #include "base/trace.hh"
 #include "debug/ProtocolTrace.hh"
 #include "debug/RubyGenerated.hh"
-#include "mem/protocol/${ident}_Controller.hh"
-#include "mem/protocol/${ident}_Event.hh"
-#include "mem/protocol/${ident}_State.hh"
-#include "mem/protocol/Types.hh"
+#include "mem/ruby/protocol/${ident}_Controller.hh"
+#include "mem/ruby/protocol/${ident}_Event.hh"
+#include "mem/ruby/protocol/${ident}_State.hh"
+#include "mem/ruby/protocol/Types.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 #define HASH_FUN(state, event)  ((int(state)*${ident}_Event_NUM)+int(event))
diff --git a/src/mem/slicc/symbols/SymbolTable.py b/src/mem/slicc/symbols/SymbolTable.py
index e991fec..e4fc0a3 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -133,7 +133,7 @@
 
         for symbol in self.sym_vec:
             if isinstance(symbol, Type) and not symbol.isPrimitive:
-                code('#include "mem/protocol/${{symbol.c_ident}}.hh"')
+                code('#include "mem/ruby/protocol/${{symbol.c_ident}}.hh"')
 
         code.write(path, "Types.hh")
 
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index e9ea618..c4d8eae 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -201,15 +201,16 @@
 #include <iostream>
 
 #include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
+
 ''')
 
         for dm in self.data_members.values():
             if not dm.type.isPrimitive:
-                code('#include "mem/protocol/$0.hh"', dm.type.c_ident)
+                code('#include "mem/ruby/protocol/$0.hh"', dm.type.c_ident)
 
         parent = ""
         if "interface" in self:
-            code('#include "mem/protocol/$0.hh"', self["interface"])
+            code('#include "mem/ruby/protocol/$0.hh"', self["interface"])
             parent = " :  public %s" % self["interface"]
 
         code('''
@@ -404,7 +405,7 @@
 #include <iostream>
 #include <memory>
 
-#include "mem/protocol/${{self.c_ident}}.hh"
+#include "mem/ruby/protocol/${{self.c_ident}}.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
 using namespace std;
@@ -456,7 +457,7 @@
 
 ''')
         if self.isStateDecl:
-            code('#include "mem/protocol/AccessPermission.hh"')
+            code('#include "mem/ruby/protocol/AccessPermission.hh"')
 
         if self.isMachineType:
             code('#include <functional>')
@@ -558,7 +559,7 @@
 #include <string>
 
 #include "base/logging.hh"
-#include "mem/protocol/${{self.c_ident}}.hh"
+#include "mem/ruby/protocol/${{self.c_ident}}.hh"
 
 using namespace std;
 
@@ -588,7 +589,8 @@
         if self.isMachineType:
             for enum in self.enums.itervalues():
                 if enum.primary:
-                    code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
+                    code('#include "mem/ruby/protocol/${{enum.ident}}'
+                            '_Controller.hh"')
             code('#include "mem/ruby/common/MachineID.hh"')
 
         code('''