src/arch/generic/BaseTLB.py

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from m5.params import *
from m5.SimObject import SimObject

class TypeTLB(ScopedEnum):
    """
    instruction: TLB contains instruction entries only
    data: TLB contains data entries only
    unified: TLB contains both instruction and data entries

    The enum values have been selected in order to perform bitwise
    operations on them. For example a unified TLB contains both
    instruction and data entries so code trying to assess if the
    TLB is storing (e.g.) data entries can do that with:

    bool has_data = tlb->type() & TypeTLB::data;
    """
    map = {
        'instruction' : 0x1,
        'data' : 0x2,
        'unified' : 0x3,
    }

class BaseTLB(SimObject):
    type = 'BaseTLB'
    abstract = True
    cxx_header = "arch/generic/tlb.hh"
    cxx_class = 'gem5::BaseTLB'

    # Ports to connect with other TLB levels
    cpu_side_ports  = VectorResponsePort("Ports closer to the CPU side")
    slave     = DeprecatedParam(cpu_side_ports,
                    '`slave` is now called `cpu_side_ports`')
    mem_side_port = RequestPort("Port closer to memory side")
    master   = DeprecatedParam(mem_side_port,
                    '`master` is now called `mem_side_port`')

    entry_type = Param.TypeTLB("Instruction/Data/Unified TLB entries")

    next_level = Param.BaseTLB(NULL, "next level")