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from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.BaseMinorCPU import BaseMinorCPU
from m5.objects.RiscvDecoder import RiscvDecoder
from m5.objects.RiscvMMU import RiscvMMU
from m5.objects.RiscvInterrupts import RiscvInterrupts
from m5.objects.RiscvISA import RiscvISA

class RiscvCPU:
    ArchDecoder = RiscvDecoder
    ArchMMU = RiscvMMU
    ArchInterrupts = RiscvInterrupts
    ArchISA = RiscvISA

class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
    mmu = RiscvMMU()

class RiscvNonCachingSimpleCPU(BaseNonCachingSimpleCPU, RiscvCPU):
    mmu = RiscvMMU()

class RiscvTimingSimpleCPU(BaseTimingSimpleCPU, RiscvCPU):
    mmu = RiscvMMU()

class RiscvO3CPU(BaseO3CPU, RiscvCPU):
    mmu = RiscvMMU()

class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
    mmu = RiscvMMU()