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from gem5.components.processors.abstract_core import AbstractCore
from gem5.isas import ISA

from .abstract_node import AbstractNode

from m5.objects import ClockDomain, RubyCache


class DMARequestor(AbstractNode):
    def __init__(self, network, cache_line_size, clk_domain: ClockDomain):
        super().__init__(network, cache_line_size)

        # Dummy cache
        self.cache = RubyCache(
            dataAccessLatency=0, tagAccessLatency=1, size="128", assoc=1
        )

        self.clk_domain = clk_domain

        # Only applies to home nodes
        self.is_HN = False
        self.enable_DMT = False
        self.enable_DCT = False

        # No cache
        self.allow_SD = False
        self.alloc_on_seq_acc = False
        self.alloc_on_seq_line_write = False
        self.alloc_on_readshared = False
        self.alloc_on_readunique = False
        self.alloc_on_readonce = False
        self.alloc_on_writeback = False
        self.dealloc_on_unique = False
        self.dealloc_on_shared = False
        self.dealloc_backinv_unique = True
        self.dealloc_backinv_shared = True

        self.send_evictions = False
        self.use_prefetcher = False
        # Some reasonable default TBE params
        self.number_of_TBEs = 16
        self.number_of_repl_TBEs = 1
        self.number_of_snoop_TBEs = 1  # Should never receive snoops
        self.number_of_DVM_TBEs = 1  # should not receive any dvm
        self.number_of_DVM_snoop_TBEs = 1  # should not receive any dvm
        self.unify_repl_TBEs = False