# Copyright (c) 2022, Fraunhofer IESE
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import os
import m5

from m5.objects import *

# Create a config to be used by the traffic generator
cfg_file_name = "memcheck.cfg"
cfg_file_path = os.path.dirname(__file__) + "/" + cfg_file_name
cfg_file = open(cfg_file_path, "w")

# Three states, with random, linear and idle behaviours. The random
# and linear states access memory in the range [0 : 16 Mbyte] with 8
# byte and 64 byte accesses respectively.
cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n")
cfg_file.write("STATE 2 10000000 IDLE\n")
cfg_file.write("INIT 0\n")
cfg_file.write("TRANSITION 0 1 0.5\n")
cfg_file.write("TRANSITION 0 2 0.5\n")
cfg_file.write("TRANSITION 1 0 0.5\n")
cfg_file.write("TRANSITION 1 2 0.5\n")
cfg_file.write("TRANSITION 2 0 0.5\n")
cfg_file.write("TRANSITION 2 1 0.5\n")
cfg_file.close()

system = System()
vd = VoltageDomain(voltage="1V")

system.mem_mode = "timing"

system.cpu = TrafficGen(config_file=cfg_file_path)
system.target = TLM_Target()
system.physmem = (
    SimpleMemory()
)  # This must be instanciated, even if not needed
# system.mem.addr_ranges = [AddrRange('512MB')]
system.transactor = Gem5ToTlmBridge32()
system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)

# Connect everything:
system.transactor.gem5 = system.cpu.port
system.transactor.tlm = system.target.tlm

kernel = SystemC_Kernel(system=system)
root = Root(full_system=False, systemc_kernel=kernel)

m5.instantiate(None)

cause = m5.simulate(m5.MaxTick).getCause()
print(cause)