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from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.SparcDecoder import SparcDecoder
from m5.objects.SparcMMU import SparcMMU
from m5.objects.SparcInterrupts import SparcInterrupts
from m5.objects.SparcISA import SparcISA

class SparcCPU:
    ArchDecoder = SparcDecoder
    ArchMMU = SparcMMU
    ArchInterrupts = SparcInterrupts
    ArchISA = SparcISA

class SparcAtomicSimpleCPU(BaseAtomicSimpleCPU, SparcCPU):
    mmu = SparcMMU()

class SparcNonCachingSimpleCPU(BaseNonCachingSimpleCPU, SparcCPU):
    mmu = SparcMMU()

class SparcTimingSimpleCPU(BaseTimingSimpleCPU, SparcCPU):
    mmu = SparcMMU()

class SparcO3CPU(BaseO3CPU, SparcCPU):
    mmu = SparcMMU()