cpu: Pull more arch specialization to the top of BaseCPU.py.
This simplifies the logic of the CPU python class, and brings us ever
so slightly closer to factoring hardcoded ISA behavior out of non-ISA
specific components.
Change-Id: I7e4511dd4e6076f5c214be5af2a0e33af0142563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19889
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 2486c2e..0e8c289 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -64,40 +64,51 @@
if buildEnv['TARGET_ISA'] == 'alpha':
from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
- from m5.objects.AlphaInterrupts import AlphaInterrupts
- from m5.objects.AlphaISA import AlphaISA
- default_isa_class = AlphaISA
+ from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
+ from m5.objects.AlphaISA import AlphaISA as ArchISA
+ ArchInterruptsParam = VectorParam.AlphaInterrupts
+ ArchISAsParam = VectorParam.AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
- from m5.objects.SparcInterrupts import SparcInterrupts
- from m5.objects.SparcISA import SparcISA
- default_isa_class = SparcISA
+ from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
+ from m5.objects.SparcISA import SparcISA as ArchISA
+ ArchInterruptsParam = VectorParam.SparcInterrupts
+ ArchISAsParam = VectorParam.SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
- from m5.objects.X86LocalApic import X86LocalApic
- from m5.objects.X86ISA import X86ISA
- default_isa_class = X86ISA
+ from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
+ from m5.objects.X86ISA import X86ISA as ArchISA
+ ArchInterruptsParam = VectorParam.X86LocalApic
+ ArchISAsParam = VectorParam.X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
- from m5.objects.MipsInterrupts import MipsInterrupts
- from m5.objects.MipsISA import MipsISA
- default_isa_class = MipsISA
+ from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
+ from m5.objects.MipsISA import MipsISA as ArchISA
+ ArchInterruptsParam = VectorParam.MipsInterrupts
+ ArchISAsParam = VectorParam.MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
- from m5.objects.ArmInterrupts import ArmInterrupts
- from m5.objects.ArmISA import ArmISA
- default_isa_class = ArmISA
+ from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
+ from m5.objects.ArmISA import ArmISA as ArchISA
+ ArchInterruptsParam = VectorParam.ArmInterrupts
+ ArchISAsParam = VectorParam.ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
- from m5.objects.PowerInterrupts import PowerInterrupts
- from m5.objects.PowerISA import PowerISA
- default_isa_class = PowerISA
+ from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
+ from m5.objects.PowerISA import PowerISA as ArchISA
+ ArchInterruptsParam = VectorParam.PowerInterrupts
+ ArchISAsParam = VectorParam.PowerISA
elif buildEnv['TARGET_ISA'] == 'riscv':
from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
- from m5.objects.RiscvInterrupts import RiscvInterrupts
- from m5.objects.RiscvISA import RiscvISA
- default_isa_class = RiscvISA
+ from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
+ from m5.objects.RiscvISA import RiscvISA as ArchISA
+ ArchInterruptsParam = VectorParam.RiscvInterrupts
+ ArchISAsParam = VectorParam.RiscvISA
+else:
+ print("Don't know what object types to use for ISA %s" %
+ buildEnv['TARGET_ISA'])
+ sys.exit(1)
class BaseCPU(ClockedObject):
type = 'BaseCPU'
@@ -171,40 +182,13 @@
dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
- if buildEnv['TARGET_ISA'] == 'sparc':
- interrupts = VectorParam.SparcInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.SparcISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'alpha':
- interrupts = VectorParam.AlphaInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.AlphaISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'x86':
- interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
- isa = VectorParam.X86ISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'mips':
- interrupts = VectorParam.MipsInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.MipsISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'arm':
+ if buildEnv['TARGET_ISA'] == 'arm':
istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
- interrupts = VectorParam.ArmInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.ArmISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
- interrupts = VectorParam.PowerInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.PowerISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'riscv':
- interrupts = VectorParam.RiscvInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.RiscvISA([], "ISA instance")
- else:
- print("Don't know what TLB to use for ISA %s" %
- buildEnv['TARGET_ISA'])
- sys.exit(1)
+ interrupts = ArchInterruptsParam([], "Interrupt Controller")
+ isa = ArchISAsParam([], "ISA instance")
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
@@ -240,25 +224,7 @@
_uncached_master_ports += ["interrupts[0].int_master"]
def createInterruptController(self):
- if buildEnv['TARGET_ISA'] == 'sparc':
- self.interrupts = [SparcInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'alpha':
- self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'x86':
- self.interrupts = [X86LocalApic() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'mips':
- self.interrupts = [MipsInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'arm':
- self.interrupts = [ArmInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'power':
- self.interrupts = [PowerInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'riscv':
- self.interrupts = \
- [RiscvInterrupts() for i in range(self.numThreads)]
- else:
- print("Don't know what Interrupt Controller to use for ISA %s" %
- buildEnv['TARGET_ISA'])
- sys.exit(1)
+ self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
def connectCachedPorts(self, bus):
for p in self._cached_ports:
@@ -312,7 +278,7 @@
# If no ISAs have been created, assume that the user wants the
# default ISA.
if len(self.isa) == 0:
- self.isa = [ default_isa_class() for i in range(self.numThreads) ]
+ self.isa = [ ArchISA() for i in range(self.numThreads) ]
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError("Number of ISA instances doesn't "
