tree 0f3f3d351882d499031c9487fcdeab24fc7cb847
parent 239054f48439c18b93e1a70ff29dbcb0c4742cff
author Gabe Black <gabeblack@google.com> 1571683433 -0700
committer Gabe Black <gabeblack@google.com> 1571870180 +0000

cpu: Apply the ARM TLB rework to the O3 checker CPU.

The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU and SimpleCPU checker already, but the TLBs
are added in the O3 checker CPU as well.

Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>