tree 5ed6c032bac38e95302279578a066fcc624e7a20
parent bee784dee932f66cefc702971a01a35f3436e929
author Ian Jiang <ianjiang.ict@gmail.com> 1572769506 +0800
committer Ian Jiang <ianjiang.ict@gmail.com> 1574645168 +0000

arch-riscv: Fix disassembling for atomic instructions

The original Gem5 does not give correct disassembly for atomic
instructions, which are implemented with one or two micro instructions.
The correct register indices are not decoded until subsequent micro
instruction is processed. This patch fixes the problem by getting the
register indices and other properties (aq and rl) from certain bitfields
of the machine code in the disassembling function.

Change-Id: I2cdaf0b3c48ff266f19ca707a5de48c9050b3897
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22568
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>