commit cee3b6ead0516727a13f37c344051d142899de60
author Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Nov 25 21:24:55 2021 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Nov 30 13:49:33 2021 +0000
tree e5219619edd8dcf13edc1a377cf2c683c4e0f12a
parent ea6b0a03d3a272abbbdf74db78bcad13651e1d79

arch-arm: Use ThreadContext when trapping MCR/MRC to cop14

We are aligning to cop15 read/writes. By passing the TC directly
we unlock the usage of TC based helper functions.

Change-Id: I1d06d31ce0bd04508f44f34cc0dcef8828d9c48c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53263
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa/insts/misc.isa

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 80ba685..7253f85 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -897,8 +897,7 @@
         return std::make_shared<UndefinedInstruction>(machInst, false,
                                                       mnemonic);
     }
-    if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
-                          Hstr, Hcptr, imm)) {
+    if (mcrMrc14TrapToHyp((MiscRegIndex) op1, xc->tcBase(), imm)) {
         return std::make_shared<HypervisorTrap>(machInst, imm,
                                                 EC_TRAPPED_CP14_MCR_MRC);
     }
@@ -922,8 +921,7 @@
         return std::make_shared<UndefinedInstruction>(machInst, false,
                                                       mnemonic);
     }
-    if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
-                          Hstr, Hcptr, imm)) {
+    if (mcrMrc14TrapToHyp(miscReg, xc->tcBase(), imm)) {
         return std::make_shared<HypervisorTrap>(machInst, imm,
                                                 EC_TRAPPED_CP14_MCR_MRC);
     }

src/arch/arm/utility.cc

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 520716e..aa223bf 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -665,8 +665,7 @@
 
 
 bool
-mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
-                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
+mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss)
 {
     bool isRead;
     uint32_t crm;
@@ -674,6 +673,14 @@
     uint32_t crn;
     uint32_t opc1;
     uint32_t opc2;
+
+    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+    const SCR scr = tc->readMiscReg(MISCREG_SCR);
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR);
+    const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
+    const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
+    const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
+
     bool trapToHype = false;
 
     if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {

src/arch/arm/utility.hh

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 0d9b3bc..46dda3a 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -302,8 +302,8 @@
 bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
                        uint32_t iss, ExceptionClass *ec=nullptr);
 
-bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
-                       HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
+bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
+                       uint32_t iss);
 
 Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
                      ThreadContext *tc, uint32_t imm);