diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py
index da686c1..256b830 100644
--- a/src/dev/arm/GenericTimer.py
+++ b/src/dev/arm/GenericTimer.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009-2020 ARM Limited
+# Copyright (c) 2009-2020, 2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -86,10 +86,10 @@
 
     counter = Param.SystemCounter(Parent.any, "Global system counter")
 
-    int_phys_s = Param.ArmPPI("Physical (S) timer interrupt")
-    int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt")
-    int_virt = Param.ArmPPI("Virtual timer interrupt")
-    int_hyp = Param.ArmPPI("Hypervisor timer interrupt")
+    int_el1_phys = Param.ArmPPI("EL1 physical timer interrupt")
+    int_el1_virt = Param.ArmPPI("EL1 virtual timer interrupt")
+    int_el2_ns_phys = Param.ArmPPI("EL2 Non-secure physical timer interrupt")
+    int_el3_phys = Param.ArmPPI("EL3 physical timer interrupt")
 
     # This value should be in theory initialized by the highest
     # priviledged software. We do this in gem5 to avoid KVM
@@ -109,10 +109,10 @@
 
         gic = self._parent.unproxy(self).gic
         node.append(FdtPropertyWords("interrupts",
-            self.int_phys_s.generateFdtProperty(gic) +
-            self.int_phys_ns.generateFdtProperty(gic) +
-            self.int_virt.generateFdtProperty(gic) +
-            self.int_hyp.generateFdtProperty(gic)))
+            self.int_el3_phys.generateFdtProperty(gic) +
+            self.int_el1_phys.generateFdtProperty(gic) +
+            self.int_el1_virt.generateFdtProperty(gic) +
+            self.int_el2_ns_phys.generateFdtProperty(gic)))
 
         if self._freq_in_dtb:
             node.append(self.counter.unproxy(self).generateDtb())
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8d6837e..4f6d7da 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009-2021 ARM Limited
+# Copyright (c) 2009-2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -832,10 +832,10 @@
 
     sys_counter = SystemCounter()
     generic_timer = GenericTimer(
-        int_phys_s=ArmPPI(num=29, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_phys_ns=ArmPPI(num=30, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_virt=ArmPPI(num=27, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_hyp=ArmPPI(num=26, int_type='IRQ_TYPE_LEVEL_LOW'))
+        int_el3_phys=ArmPPI(num=29, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el1_phys=ArmPPI(num=30, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el1_virt=ArmPPI(num=27, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el2_ns_phys=ArmPPI(num=26, int_type='IRQ_TYPE_LEVEL_LOW'))
 
     timer0 = Sp804(int0=ArmSPI(num=34), int1=ArmSPI(num=34),
                    pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
@@ -1045,11 +1045,11 @@
       0- 15: Software generated interrupts (SGIs)
      16- 31: On-chip private peripherals (PPIs)
         25   : vgic
-        26   : generic_timer (hyp)
-        27   : generic_timer (virt)
+        26   : generic_timer (phys non-sec EL2)
+        27   : generic_timer (virt EL1)
         28   : Reserved (Legacy FIQ)
-        29   : generic_timer (phys, sec)
-        30   : generic_timer (phys, non-sec)
+        29   : generic_timer (phys EL3)
+        30   : generic_timer (phys EL1)
         31   : Reserved (Legacy IRQ)
     32- 95: Mother board peripherals (SPIs)
         32   : Watchdog (SP805)
@@ -1125,10 +1125,10 @@
 
     sys_counter = SystemCounter()
     generic_timer = GenericTimer(
-        int_phys_s=ArmPPI(num=29, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_phys_ns=ArmPPI(num=30, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_virt=ArmPPI(num=27, int_type='IRQ_TYPE_LEVEL_LOW'),
-        int_hyp=ArmPPI(num=26, int_type='IRQ_TYPE_LEVEL_LOW'))
+        int_el3_phys=ArmPPI(num=29, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el1_phys=ArmPPI(num=30, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el1_virt=ArmPPI(num=27, int_type='IRQ_TYPE_LEVEL_LOW'),
+        int_el2_ns_phys=ArmPPI(num=26, int_type='IRQ_TYPE_LEVEL_LOW'))
     generic_timer_mem = GenericTimerMem(cnt_control_base=0x2a430000,
                                         cnt_read_base=0x2a800000,
                                         cnt_ctl_base=0x2a810000,
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 8377b94..2eba1e7 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015, 2017-2018,2020 ARM Limited
+ * Copyright (c) 2013, 2015, 2017-2018,2020,2022 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -495,10 +495,10 @@
 
         timers[i].reset(
             new CoreTimers(*this, system, i,
-                           p.int_phys_s->get(tc),
-                           p.int_phys_ns->get(tc),
-                           p.int_virt->get(tc),
-                           p.int_hyp->get(tc)));
+                           p.int_el3_phys->get(tc),
+                           p.int_el1_phys->get(tc),
+                           p.int_el1_virt->get(tc),
+                           p.int_el2_ns_phys->get(tc)));
     }
 }
 
@@ -551,7 +551,7 @@
         RegVal old_cnt_ctl = core.cntkctl;
         core.cntkctl = val;
 
-        ArchTimer *timer = &core.virt;
+        ArchTimer *timer = &core.virtEL1;
         CoreTimers::EventStream *ev_stream = &core.virtEvStream;
 
         handleStream(ev_stream, timer, old_cnt_ctl, val);
@@ -563,26 +563,26 @@
         RegVal old_cnt_ctl = core.cnthctl;
         core.cnthctl = val;
 
-        ArchTimer *timer = &core.physNS;
+        ArchTimer *timer = &core.physEL1;
         CoreTimers::EventStream *ev_stream = &core.physEvStream;
 
         handleStream(ev_stream, timer, old_cnt_ctl, val);
         return;
       }
-      // Physical timer (NS)
+      // EL1 physical timer
       case MISCREG_CNTP_CVAL_NS:
       case MISCREG_CNTP_CVAL_EL0:
-        core.physNS.setCompareValue(val);
+        core.physEL1.setCompareValue(val);
         return;
 
       case MISCREG_CNTP_TVAL_NS:
       case MISCREG_CNTP_TVAL_EL0:
-        core.physNS.setTimerValue(val);
+        core.physEL1.setTimerValue(val);
         return;
 
       case MISCREG_CNTP_CTL_NS:
       case MISCREG_CNTP_CTL_EL0:
-        core.physNS.setControl(val);
+        core.physEL1.setControl(val);
         return;
 
       // Count registers
@@ -594,57 +594,57 @@
              miscRegName[reg]);
         return;
 
-      // Virtual timer
+      // EL1 virtual timer
       case MISCREG_CNTVOFF:
       case MISCREG_CNTVOFF_EL2:
-        core.virt.setOffset(val);
+        core.virtEL1.setOffset(val);
         return;
 
       case MISCREG_CNTV_CVAL:
       case MISCREG_CNTV_CVAL_EL0:
-        core.virt.setCompareValue(val);
+        core.virtEL1.setCompareValue(val);
         return;
 
       case MISCREG_CNTV_TVAL:
       case MISCREG_CNTV_TVAL_EL0:
-        core.virt.setTimerValue(val);
+        core.virtEL1.setTimerValue(val);
         return;
 
       case MISCREG_CNTV_CTL:
       case MISCREG_CNTV_CTL_EL0:
-        core.virt.setControl(val);
+        core.virtEL1.setControl(val);
         return;
 
-      // Physical timer (S)
+      // EL3 physical timer
       case MISCREG_CNTP_CTL_S:
       case MISCREG_CNTPS_CTL_EL1:
-        core.physS.setControl(val);
+        core.physEL3.setControl(val);
         return;
 
       case MISCREG_CNTP_CVAL_S:
       case MISCREG_CNTPS_CVAL_EL1:
-        core.physS.setCompareValue(val);
+        core.physEL3.setCompareValue(val);
         return;
 
       case MISCREG_CNTP_TVAL_S:
       case MISCREG_CNTPS_TVAL_EL1:
-        core.physS.setTimerValue(val);
+        core.physEL3.setTimerValue(val);
         return;
 
-      // Hyp phys. timer, non-secure
+      // EL2 Non-secure physical timer
       case MISCREG_CNTHP_CTL:
       case MISCREG_CNTHP_CTL_EL2:
-        core.hyp.setControl(val);
+        core.physNsEL2.setControl(val);
         return;
 
       case MISCREG_CNTHP_CVAL:
       case MISCREG_CNTHP_CVAL_EL2:
-        core.hyp.setCompareValue(val);
+        core.physNsEL2.setCompareValue(val);
         return;
 
       case MISCREG_CNTHP_TVAL:
       case MISCREG_CNTHP_TVAL_EL2:
-        core.hyp.setTimerValue(val);
+        core.physNsEL2.setTimerValue(val);
         return;
 
       default:
@@ -669,70 +669,70 @@
       case MISCREG_CNTHCTL:
       case MISCREG_CNTHCTL_EL2:
         return core.cnthctl & 0x00000000ffffffff;
-      // Physical timer
+      // EL1 physical timer
       case MISCREG_CNTP_CVAL_NS:
       case MISCREG_CNTP_CVAL_EL0:
-        return core.physNS.compareValue();
+        return core.physEL1.compareValue();
 
       case MISCREG_CNTP_TVAL_NS:
       case MISCREG_CNTP_TVAL_EL0:
-        return core.physNS.timerValue();
+        return core.physEL1.timerValue();
 
       case MISCREG_CNTP_CTL_EL0:
       case MISCREG_CNTP_CTL_NS:
-        return core.physNS.control();
+        return core.physEL1.control();
 
       case MISCREG_CNTPCT:
       case MISCREG_CNTPCT_EL0:
-        return core.physNS.value();
+        return core.physEL1.value();
 
 
-      // Virtual timer
+      // EL1 virtual timer
       case MISCREG_CNTVCT:
       case MISCREG_CNTVCT_EL0:
-        return core.virt.value();
+        return core.virtEL1.value();
 
       case MISCREG_CNTVOFF:
       case MISCREG_CNTVOFF_EL2:
-        return core.virt.offset();
+        return core.virtEL1.offset();
 
       case MISCREG_CNTV_CVAL:
       case MISCREG_CNTV_CVAL_EL0:
-        return core.virt.compareValue();
+        return core.virtEL1.compareValue();
 
       case MISCREG_CNTV_TVAL:
       case MISCREG_CNTV_TVAL_EL0:
-        return core.virt.timerValue();
+        return core.virtEL1.timerValue();
 
       case MISCREG_CNTV_CTL:
       case MISCREG_CNTV_CTL_EL0:
-        return core.virt.control();
+        return core.virtEL1.control();
 
-      // PL1 phys. timer, secure
+      // EL3 physical timer
       case MISCREG_CNTP_CTL_S:
       case MISCREG_CNTPS_CTL_EL1:
-        return core.physS.control();
+        return core.physEL3.control();
 
       case MISCREG_CNTP_CVAL_S:
       case MISCREG_CNTPS_CVAL_EL1:
-        return core.physS.compareValue();
+        return core.physEL3.compareValue();
 
       case MISCREG_CNTP_TVAL_S:
       case MISCREG_CNTPS_TVAL_EL1:
-        return core.physS.timerValue();
+        return core.physEL3.timerValue();
 
-      // HYP phys. timer (NS)
+      // EL2 Non-secure physical timer
       case MISCREG_CNTHP_CTL:
       case MISCREG_CNTHP_CTL_EL2:
-        return core.hyp.control();
+        return core.physNsEL2.control();
 
       case MISCREG_CNTHP_CVAL:
       case MISCREG_CNTHP_CVAL_EL2:
-        return core.hyp.compareValue();
+        return core.physNsEL2.compareValue();
 
       case MISCREG_CNTHP_TVAL:
       case MISCREG_CNTHP_TVAL_EL2:
-        return core.hyp.timerValue();
+        return core.physNsEL2.timerValue();
 
       default:
         warn("Reading from unknown register: %s\n", miscRegName[reg]);
@@ -742,30 +742,28 @@
 
 GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
     ArmSystem &system, unsigned cpu,
-    ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
-    ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
+    ArmInterruptPin *irq_el3_phys, ArmInterruptPin *irq_el1_phys,
+    ArmInterruptPin *irq_el1_virt, ArmInterruptPin *irq_el2_ns_phys)
       : parent(_parent),
         cntfrq(parent.params().cntfrq),
         cntkctl(0), cnthctl(0),
         threadContext(system.threads[cpu]),
-        irqPhysS(_irqPhysS),
-        irqPhysNS(_irqPhysNS),
-        irqVirt(_irqVirt),
-        irqHyp(_irqHyp),
-        physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
-              system, parent, parent.systemCounter,
-              _irqPhysS),
-        // This should really be phys_timerN, but we are stuck with
-        // arch_timer for backwards compatibility.
-        physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
-             system, parent, parent.systemCounter,
-             _irqPhysNS),
-        virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
-           system, parent, parent.systemCounter,
-           _irqVirt),
-        hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
-           system, parent, parent.systemCounter,
-           _irqHyp),
+        irqPhysEL3(irq_el3_phys),
+        irqPhysEL1(irq_el1_phys),
+        irqVirtEL1(irq_el1_virt),
+        irqPhysNsEL2(irq_el2_ns_phys),
+        physEL3(csprintf("%s.el3_phys_timer%d", parent.name(), cpu),
+                system, parent, parent.systemCounter,
+                irq_el3_phys),
+        physEL1(csprintf("%s.el1_phys_timer%d", parent.name(), cpu),
+                system, parent, parent.systemCounter,
+                irq_el1_phys),
+        virtEL1(csprintf("%s.el1_virt_timer%d", parent.name(), cpu),
+                system, parent, parent.systemCounter,
+                irq_el1_virt),
+        physNsEL2(csprintf("%s.el2_ns_phys_timer%d", parent.name(), cpu),
+                  system, parent, parent.systemCounter,
+                  irq_el2_ns_phys),
         physEvStream{
            EventFunctionWrapper([this]{ physEventStreamCallback(); },
            csprintf("%s.phys_event_gen%d", parent.name(), cpu)), 0, 0
@@ -781,14 +779,14 @@
 GenericTimer::CoreTimers::physEventStreamCallback()
 {
     eventStreamCallback();
-    schedNextEvent(physEvStream, physNS);
+    schedNextEvent(physEvStream, physEL1);
 }
 
 void
 GenericTimer::CoreTimers::virtEventStreamCallback()
 {
     eventStreamCallback();
-    schedNextEvent(virtEvStream, virt);
+    schedNextEvent(virtEvStream, virtEL1);
 }
 
 void
@@ -809,8 +807,8 @@
 void
 GenericTimer::CoreTimers::notify()
 {
-    schedNextEvent(virtEvStream, virt);
-    schedNextEvent(physEvStream, physNS);
+    schedNextEvent(virtEvStream, virtEL1);
+    schedNextEvent(physEvStream, physEL1);
 }
 
 void
@@ -838,10 +836,10 @@
     SERIALIZE_SCALAR(virtEvStream.transitionTo);
     SERIALIZE_SCALAR(virtEvStream.transitionBit);
 
-    physS.serializeSection(cp, "phys_s_timer");
-    physNS.serializeSection(cp, "phys_ns_timer");
-    virt.serializeSection(cp, "virt_timer");
-    hyp.serializeSection(cp, "hyp_timer");
+    physEL3.serializeSection(cp, "phys_el3_timer");
+    physEL1.serializeSection(cp, "phys_el1_timer");
+    virtEL1.serializeSection(cp, "virt_el1_timer");
+    physNsEL2.serializeSection(cp, "phys_ns_el2_timer");
 }
 
 void
@@ -871,10 +869,10 @@
     UNSERIALIZE_SCALAR(virtEvStream.transitionTo);
     UNSERIALIZE_SCALAR(virtEvStream.transitionBit);
 
-    physS.unserializeSection(cp, "phys_s_timer");
-    physNS.unserializeSection(cp, "phys_ns_timer");
-    virt.unserializeSection(cp, "virt_timer");
-    hyp.unserializeSection(cp, "hyp_timer");
+    physEL3.unserializeSection(cp, "phys_el3_timer");
+    physEL1.unserializeSection(cp, "phys_el1_timer");
+    virtEL1.unserializeSection(cp, "virt_el1_timer");
+    physNsEL2.unserializeSection(cp, "phys_ns_el2_timer");
 }
 
 void
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index cf04dad..2ef71f5 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015, 2017-2018,2020 ARM Limited
+ * Copyright (c) 2013, 2015, 2017-2018,2020,2022 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -302,8 +302,10 @@
     {
       public:
         CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu,
-                   ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
-                   ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp);
+                   ArmInterruptPin *irq_el3_phys,
+                   ArmInterruptPin *irq_el1_phys,
+                   ArmInterruptPin *irq_el1_virt,
+                   ArmInterruptPin *irq_el2_ns_phys);
 
         /// Generic Timer parent reference
         GenericTimer &parent;
@@ -320,15 +322,15 @@
         /// Thread (HW) context associated to this PE implementation
         ThreadContext *threadContext;
 
-        ArmInterruptPin const *irqPhysS;
-        ArmInterruptPin const *irqPhysNS;
-        ArmInterruptPin const *irqVirt;
-        ArmInterruptPin const *irqHyp;
+        ArmInterruptPin const *irqPhysEL3;
+        ArmInterruptPin const *irqPhysEL1;
+        ArmInterruptPin const *irqVirtEL1;
+        ArmInterruptPin const *irqPhysNsEL2;
 
-        ArchTimerKvm physS;
-        ArchTimerKvm physNS;
-        ArchTimerKvm virt;
-        ArchTimerKvm hyp;
+        ArchTimerKvm physEL3;
+        ArchTimerKvm physEL1;
+        ArchTimerKvm virtEL1;
+        ArchTimerKvm physNsEL2;
 
         // Event Stream. Events are generated based on a configurable
         // transitionBit over the counter value. transitionTo indicates