79bab1dc5d5af3c368030a04a46d7443b71d6513 - public/gem5

commit	79bab1dc5d5af3c368030a04a46d7443b71d6513	[log] [tgz]
author	Daniel R. Carvalho <odanrc@yahoo.com.br>	Sun Jun 13 12:05:03 2021 -0300
committer	Daniel Carvalho <odanrc@yahoo.com.br>	Fri Jul 09 11:24:10 2021 +0000
tree	b19158e65c7884f12c26d1bb588d476b36a38ca9
parent	5635b3aaa284636f9c38ef034aedc35751bf07bf [diff]

mem: Adopt a memory namespace for memories

Encapsulate every class inheriting from Abstract or Physical
memories, and the memory controller in a memory namespace.

Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47309
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/arch/arm/semihosting.cc[diff]
src/cpu/kvm/vm.cc[diff]
src/cpu/o3/inst_queue.hh[diff]
src/mem/AbstractMemory.py[diff]
src/mem/CfiMemory.py[diff]
src/mem/DRAMInterface.py[diff]
src/mem/DRAMSim2.py[diff]
src/mem/DRAMsim3.py[diff]
src/mem/MemCtrl.py[diff]
src/mem/MemInterface.py[diff]
src/mem/NVMInterface.py[diff]
src/mem/SimpleMemory.py[diff]
src/mem/abstract_mem.cc[diff]
src/mem/abstract_mem.hh[diff]
src/mem/cfi_mem.cc[diff]
src/mem/cfi_mem.hh[diff]
src/mem/dramsim2.cc[diff]
src/mem/dramsim2.hh[diff]
src/mem/dramsim2_wrapper.cc[diff]
src/mem/dramsim2_wrapper.hh[diff]
src/mem/dramsim3.cc[diff]
src/mem/dramsim3.hh[diff]
src/mem/dramsim3_wrapper.cc[diff]
src/mem/dramsim3_wrapper.hh[diff]
src/mem/mem_ctrl.cc[diff]
src/mem/mem_ctrl.hh[diff]
src/mem/mem_interface.cc[diff]
src/mem/mem_interface.hh[diff]
src/mem/physical.cc[diff]
src/mem/physical.hh[diff]
src/mem/ruby/system/RubySystem.hh[diff]
src/mem/simple_mem.cc[diff]
src/mem/simple_mem.hh[diff]
src/sim/system.cc[diff]
src/sim/system.hh[diff]

35 files changed

tree: b19158e65c7884f12c26d1bb588d476b36a38ca9