tree 45351a6259360780f3d58a5325ba7ebcf8cc5d8d
parent b39c106eea6ecd768fe120820f1eedd2e73128a9
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1639494831 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1639645253 +0000

configs: Stop using a PTW cache before L2 in Arm configs

This implementation of a walk cache does not allow to skip walks as it
is a simple cache placed in front of the table walker.
It was meant to provide a faster retrieval of page table descriptors
than fetching them from L2 or memory.

This is not needed anymore for Arm as from [1] we implement
partial translation caching in Arm TLBs.

[1]: JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I00d44a4e3961e15602bf4352f2f42ddccf2b746b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54243
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>