commit d342e0309531788424777a4de52ba11069857475
author Bobby R. Bruce <bbruce@ucdavis.edu> Mon May 25 14:24:34 2020 -0700
committer Bobby R. Bruce <bbruce@ucdavis.edu> Wed May 27 07:07:04 2020 +0000
tree cd8cce481a5079dc761ad2d3629e18facc66352e
parent 77482d59a511d1e741185c9d5a6c87edead7e8bb

arch-riscv,misc: Added M5_VAR_USED to MiscRegNames

Clang compilers return an error about MiscRegNames being unused.
M5_VAR_USED fixes this.

Change-Id: I515c5d1e8837020b674de49039c0525f896b7e37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/isa.cc

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ac26230..055c95b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -38,6 +38,7 @@
 #include "arch/riscv/pagetable.hh"
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "cpu/base.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/RiscvMisc.hh"
@@ -48,7 +49,7 @@
 namespace RiscvISA
 {
 
-const std::array<const char *, NumMiscRegs> MiscRegNames = {{
+const std::array<const char *, NumMiscRegs> M5_VAR_USED MiscRegNames = {{
     [MISCREG_PRV]           = "PRV",
     [MISCREG_ISA]           = "ISA",
     [MISCREG_VENDORID]      = "VENDORID",