)]}'
{
  "commit": "d54b8f8475495213f5c2e69aadd7886c69bcd53c",
  "tree": "c6135a407d0cc01b84944e368c083b7b51335347",
  "parents": [
    "b182b15f93621206c87c6c760cdfc1f5df1877cf"
  ],
  "author": {
    "name": "Adrià Armejach",
    "email": "adria.armejach@bsc.es",
    "time": "Wed Jun 07 17:01:03 2023 +0200"
  },
  "committer": {
    "name": "Bobby Bruce",
    "email": "bbruce@ucdavis.edu",
    "time": "Fri Jun 16 16:44:49 2023 +0000"
  },
  "message": "arch-riscv: fix load reserved store conditional\n\n  * According to the manual, load reservations must be cleared on a\n    failed or a successful SC attempt.\n  * A load reservation can be arbitrarily large. The current\n    implementation was reserving something different than cacheBlockSize\n    which could lead to problems if snoop addresses are cache block\n    aligned. This patch implementation assumes a cacheBlock granularity.\n  * Load reservations should also be cleared on faults\n\nChange-Id: I64513534710b5f269260fcb204f717801913e2f5\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71520\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n",
  "tree_diff": [
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}