| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| exit_on_work_items=false |
| init_param=0 |
| kernel= |
| kernel_addr_check=true |
| load_addr_mask=1099511627775 |
| load_offset=0 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| mmap_using_noreserve=false |
| multi_thread=false |
| num_work_ids=16 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| readfile= |
| symbolfile= |
| thermal_components= |
| thermal_model=Null |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[0] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| clock=1000 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.cpu] |
| type=MinorCPU |
| children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload |
| branchPred=system.cpu.branchPred |
| checker=Null |
| clk_domain=system.cpu_clk_domain |
| cpu_id=0 |
| decodeCycleInput=true |
| decodeInputBufferSize=3 |
| decodeInputWidth=2 |
| decodeToExecuteForwardDelay=1 |
| default_p_state=UNDEFINED |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dstage2_mmu=system.cpu.dstage2_mmu |
| dtb=system.cpu.dtb |
| enableIdling=true |
| eventq_index=0 |
| executeAllowEarlyMemoryIssue=true |
| executeBranchDelay=1 |
| executeCommitLimit=2 |
| executeCycleInput=true |
| executeFuncUnits=system.cpu.executeFuncUnits |
| executeInputBufferSize=7 |
| executeInputWidth=2 |
| executeIssueLimit=2 |
| executeLSQMaxStoreBufferStoresPerCycle=2 |
| executeLSQRequestsQueueSize=1 |
| executeLSQStoreBufferSize=5 |
| executeLSQTransfersQueueSize=2 |
| executeMaxAccessesInMemory=2 |
| executeMemoryCommitLimit=1 |
| executeMemoryIssueLimit=1 |
| executeMemoryWidth=0 |
| executeSetTraceTimeOnCommit=true |
| executeSetTraceTimeOnIssue=false |
| fetch1FetchLimit=1 |
| fetch1LineSnapWidth=0 |
| fetch1LineWidth=0 |
| fetch1ToFetch2BackwardDelay=1 |
| fetch1ToFetch2ForwardDelay=1 |
| fetch2CycleInput=true |
| fetch2InputBufferSize=2 |
| fetch2ToDecodeForwardDelay=1 |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu.interrupts |
| isa=system.cpu.isa |
| istage2_mmu=system.cpu.istage2_mmu |
| itb=system.cpu.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| profile=0 |
| progress_interval=0 |
| simpoint_start_insts= |
| socket_id=0 |
| switched_out=false |
| syscallRetryLatency=10000 |
| system=system |
| threadPolicy=RoundRobin |
| tracer=system.cpu.tracer |
| workload=system.cpu.workload |
| dcache_port=system.cpu.dcache.cpu_side |
| icache_port=system.cpu.icache.cpu_side |
| |
| [system.cpu.branchPred] |
| type=TournamentBP |
| BTBEntries=4096 |
| BTBTagSize=16 |
| RASSize=16 |
| choiceCtrBits=2 |
| choicePredictorSize=8192 |
| eventq_index=0 |
| globalCtrBits=2 |
| globalPredictorSize=8192 |
| indirectHashGHR=true |
| indirectHashTargets=true |
| indirectPathLength=3 |
| indirectSets=256 |
| indirectTagSize=16 |
| indirectWays=2 |
| instShiftAmt=2 |
| localCtrBits=2 |
| localHistoryTableSize=2048 |
| localPredictorSize=2048 |
| numThreads=1 |
| useIndirect=true |
| |
| [system.cpu.dcache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_incl |
| data_latency=2 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=4 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=262144 |
| system=system |
| tag_latency=2 |
| tags=system.cpu.dcache.tags |
| tgts_per_mshr=20 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.cpu.dcache_port |
| mem_side=system.cpu.toL2Bus.slave[1] |
| |
| [system.cpu.dcache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=2 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=262144 |
| tag_latency=2 |
| |
| [system.cpu.dstage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.dtb |
| |
| [system.cpu.dstage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.dstage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.dstage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.dtb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.dtb.walker |
| |
| [system.cpu.dtb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.cpu.toL2Bus.slave[3] |
| |
| [system.cpu.executeFuncUnits] |
| type=MinorFUPool |
| children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 |
| eventq_index=0 |
| funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 |
| |
| [system.cpu.executeFuncUnits.funcUnits0] |
| type=MinorFU |
| children=opClasses timings |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses |
| opLat=3 |
| timings=system.cpu.executeFuncUnits.funcUnits0.timings |
| |
| [system.cpu.executeFuncUnits.funcUnits0.opClasses] |
| type=MinorOpClassSet |
| children=opClasses |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses |
| |
| [system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=IntAlu |
| |
| [system.cpu.executeFuncUnits.funcUnits0.timings] |
| type=MinorFUTiming |
| children=opClasses |
| description=Int |
| eventq_index=0 |
| extraAssumedLat=0 |
| extraCommitLat=0 |
| extraCommitLatExpr=Null |
| mask=0 |
| match=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses |
| srcRegsRelativeLats=2 |
| suppress=false |
| |
| [system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] |
| type=MinorOpClassSet |
| eventq_index=0 |
| opClasses= |
| |
| [system.cpu.executeFuncUnits.funcUnits1] |
| type=MinorFU |
| children=opClasses timings |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses |
| opLat=3 |
| timings=system.cpu.executeFuncUnits.funcUnits1.timings |
| |
| [system.cpu.executeFuncUnits.funcUnits1.opClasses] |
| type=MinorOpClassSet |
| children=opClasses |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses |
| |
| [system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=IntAlu |
| |
| [system.cpu.executeFuncUnits.funcUnits1.timings] |
| type=MinorFUTiming |
| children=opClasses |
| description=Int |
| eventq_index=0 |
| extraAssumedLat=0 |
| extraCommitLat=0 |
| extraCommitLatExpr=Null |
| mask=0 |
| match=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses |
| srcRegsRelativeLats=2 |
| suppress=false |
| |
| [system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] |
| type=MinorOpClassSet |
| eventq_index=0 |
| opClasses= |
| |
| [system.cpu.executeFuncUnits.funcUnits2] |
| type=MinorFU |
| children=opClasses timings |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses |
| opLat=3 |
| timings=system.cpu.executeFuncUnits.funcUnits2.timings |
| |
| [system.cpu.executeFuncUnits.funcUnits2.opClasses] |
| type=MinorOpClassSet |
| children=opClasses |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses |
| |
| [system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=IntMult |
| |
| [system.cpu.executeFuncUnits.funcUnits2.timings] |
| type=MinorFUTiming |
| children=opClasses |
| description=Mul |
| eventq_index=0 |
| extraAssumedLat=0 |
| extraCommitLat=0 |
| extraCommitLatExpr=Null |
| mask=0 |
| match=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses |
| srcRegsRelativeLats=0 |
| suppress=false |
| |
| [system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] |
| type=MinorOpClassSet |
| eventq_index=0 |
| opClasses= |
| |
| [system.cpu.executeFuncUnits.funcUnits3] |
| type=MinorFU |
| children=opClasses |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=9 |
| opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses |
| opLat=9 |
| timings= |
| |
| [system.cpu.executeFuncUnits.funcUnits3.opClasses] |
| type=MinorOpClassSet |
| children=opClasses |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses |
| |
| [system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=IntDiv |
| |
| [system.cpu.executeFuncUnits.funcUnits4] |
| type=MinorFU |
| children=opClasses timings |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses |
| opLat=6 |
| timings=system.cpu.executeFuncUnits.funcUnits4.timings |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses] |
| type=MinorOpClassSet |
| children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatAdd |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatCmp |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatCvt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatMisc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatMult |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatMultAcc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatDiv |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatSqrt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdAdd |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdAddAcc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdAlu |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdCmp |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdCvt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdMisc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdMult |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdMultAcc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdShift |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdShiftAcc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdSqrt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatAdd |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatAlu |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatCmp |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatCvt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatDiv |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatMisc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatMult |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatMultAcc |
| |
| [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=SimdFloatSqrt |
| |
| [system.cpu.executeFuncUnits.funcUnits4.timings] |
| type=MinorFUTiming |
| children=opClasses |
| description=FloatSimd |
| eventq_index=0 |
| extraAssumedLat=0 |
| extraCommitLat=0 |
| extraCommitLatExpr=Null |
| mask=0 |
| match=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses |
| srcRegsRelativeLats=2 |
| suppress=false |
| |
| [system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] |
| type=MinorOpClassSet |
| eventq_index=0 |
| opClasses= |
| |
| [system.cpu.executeFuncUnits.funcUnits5] |
| type=MinorFU |
| children=opClasses timings |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses |
| opLat=1 |
| timings=system.cpu.executeFuncUnits.funcUnits5.timings |
| |
| [system.cpu.executeFuncUnits.funcUnits5.opClasses] |
| type=MinorOpClassSet |
| children=opClasses0 opClasses1 opClasses2 opClasses3 |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 |
| |
| [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=MemRead |
| |
| [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=MemWrite |
| |
| [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatMemRead |
| |
| [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=FloatMemWrite |
| |
| [system.cpu.executeFuncUnits.funcUnits5.timings] |
| type=MinorFUTiming |
| children=opClasses |
| description=Mem |
| eventq_index=0 |
| extraAssumedLat=2 |
| extraCommitLat=0 |
| extraCommitLatExpr=Null |
| mask=0 |
| match=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses |
| srcRegsRelativeLats=1 |
| suppress=false |
| |
| [system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] |
| type=MinorOpClassSet |
| eventq_index=0 |
| opClasses= |
| |
| [system.cpu.executeFuncUnits.funcUnits6] |
| type=MinorFU |
| children=opClasses |
| cantForwardFromFUIndices= |
| eventq_index=0 |
| issueLat=1 |
| opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses |
| opLat=1 |
| timings= |
| |
| [system.cpu.executeFuncUnits.funcUnits6.opClasses] |
| type=MinorOpClassSet |
| children=opClasses0 opClasses1 |
| eventq_index=0 |
| opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 |
| |
| [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=IprAccess |
| |
| [system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] |
| type=MinorOpClass |
| eventq_index=0 |
| opClass=InstPrefetch |
| |
| [system.cpu.icache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_incl |
| data_latency=2 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=true |
| max_miss_count=0 |
| mshrs=4 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=131072 |
| system=system |
| tag_latency=2 |
| tags=system.cpu.icache.tags |
| tgts_per_mshr=20 |
| write_buffers=8 |
| writeback_clean=true |
| cpu_side=system.cpu.icache_port |
| mem_side=system.cpu.toL2Bus.slave[0] |
| |
| [system.cpu.icache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=2 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=131072 |
| tag_latency=2 |
| |
| [system.cpu.interrupts] |
| type=ArmInterrupts |
| eventq_index=0 |
| |
| [system.cpu.isa] |
| type=ArmISA |
| decoderFlavour=Generic |
| eventq_index=0 |
| fpsid=1090793632 |
| id_aa64afr0_el1=0 |
| id_aa64afr1_el1=0 |
| id_aa64dfr0_el1=1052678 |
| id_aa64dfr1_el1=0 |
| id_aa64isar0_el1=0 |
| id_aa64isar1_el1=0 |
| id_aa64mmfr0_el1=15728642 |
| id_aa64mmfr1_el1=0 |
| id_isar0=34607377 |
| id_isar1=34677009 |
| id_isar2=555950401 |
| id_isar3=17899825 |
| id_isar4=268501314 |
| id_isar5=0 |
| id_mmfr0=270536963 |
| id_mmfr1=0 |
| id_mmfr2=19070976 |
| id_mmfr3=34611729 |
| midr=1091551472 |
| pmu=Null |
| system=system |
| |
| [system.cpu.istage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.itb |
| |
| [system.cpu.istage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.istage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.istage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.itb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.itb.walker |
| |
| [system.cpu.itb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.cpu.toL2Bus.slave[2] |
| |
| [system.cpu.l2cache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=8 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_incl |
| data_latency=20 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=20 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=20 |
| sequential_access=false |
| size=2097152 |
| system=system |
| tag_latency=20 |
| tags=system.cpu.l2cache.tags |
| tgts_per_mshr=12 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.cpu.toL2Bus.master[0] |
| mem_side=system.membus.slave[1] |
| |
| [system.cpu.l2cache.tags] |
| type=LRU |
| assoc=8 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=20 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=2097152 |
| tag_latency=20 |
| |
| [system.cpu.toL2Bus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=0 |
| frontend_latency=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=false |
| power_model=Null |
| response_latency=1 |
| snoop_filter=system.cpu.toL2Bus.snoop_filter |
| snoop_response_latency=1 |
| system=system |
| use_default_range=false |
| width=32 |
| master=system.cpu.l2cache.cpu_side |
| slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| |
| [system.cpu.toL2Bus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=0 |
| max_capacity=8388608 |
| system=system |
| |
| [system.cpu.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.workload] |
| type=Process |
| cmd=hello |
| cwd= |
| drivers= |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| eventq_index=0 |
| executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello |
| gid=100 |
| input=cin |
| kvmInSE=false |
| maxStackSize=67108864 |
| output=cout |
| pgid=100 |
| pid=100 |
| ppid=0 |
| simpoint=0 |
| system=system |
| uid=100 |
| useArchPT=false |
| |
| [system.cpu_clk_domain] |
| type=SrcClockDomain |
| clock=500 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.dvfs_handler] |
| type=DVFSHandler |
| domains= |
| enable=false |
| eventq_index=0 |
| sys_clk_domain=system.clk_domain |
| transition_latency=100000000 |
| |
| [system.membus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=4 |
| frontend_latency=3 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=true |
| power_model=Null |
| response_latency=2 |
| snoop_filter=system.membus.snoop_filter |
| snoop_response_latency=4 |
| system=system |
| use_default_range=false |
| width=16 |
| master=system.physmem.port |
| slave=system.system_port system.cpu.l2cache.mem_side |
| |
| [system.membus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=1 |
| max_capacity=8388608 |
| system=system |
| |
| [system.physmem] |
| type=DRAMCtrl |
| IDD0=0.055000 |
| IDD02=0.000000 |
| IDD2N=0.032000 |
| IDD2N2=0.000000 |
| IDD2P0=0.000000 |
| IDD2P02=0.000000 |
| IDD2P1=0.032000 |
| IDD2P12=0.000000 |
| IDD3N=0.038000 |
| IDD3N2=0.000000 |
| IDD3P0=0.000000 |
| IDD3P02=0.000000 |
| IDD3P1=0.038000 |
| IDD3P12=0.000000 |
| IDD4R=0.157000 |
| IDD4R2=0.000000 |
| IDD4W=0.125000 |
| IDD4W2=0.000000 |
| IDD5=0.235000 |
| IDD52=0.000000 |
| IDD6=0.020000 |
| IDD62=0.000000 |
| VDD=1.500000 |
| VDD2=0.000000 |
| activation_limit=4 |
| addr_mapping=RoRaBaCoCh |
| bank_groups_per_rank=0 |
| banks_per_rank=8 |
| burst_length=8 |
| channels=1 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| default_p_state=UNDEFINED |
| device_bus_width=8 |
| device_rowbuffer_size=1024 |
| device_size=536870912 |
| devices_per_rank=8 |
| dll=true |
| eventq_index=0 |
| in_addr_map=true |
| kvm_map=true |
| max_accesses_per_row=16 |
| mem_sched_policy=frfcfs |
| min_writes_per_switch=16 |
| null=false |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| page_policy=open_adaptive |
| power_model=Null |
| range=0:134217727:0:0:0:0 |
| ranks_per_channel=2 |
| read_buffer_size=32 |
| static_backend_latency=10000 |
| static_frontend_latency=10000 |
| tBURST=5000 |
| tCCD_L=0 |
| tCK=1250 |
| tCL=13750 |
| tCS=2500 |
| tRAS=35000 |
| tRCD=13750 |
| tREFI=7800000 |
| tRFC=260000 |
| tRP=13750 |
| tRRD=6000 |
| tRRD_L=0 |
| tRTP=7500 |
| tRTW=2500 |
| tWR=15000 |
| tWTR=7500 |
| tXAW=30000 |
| tXP=6000 |
| tXPDLL=0 |
| tXS=270000 |
| tXSDLL=0 |
| write_buffer_size=64 |
| write_high_thresh_perc=85 |
| write_low_thresh_perc=50 |
| port=system.membus.master[0] |
| |
| [system.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
