| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000033 |
| sim_ticks 32617500 |
| final_tick 32617500 |
| sim_freq 1000000000000 |
| host_inst_rate 73373 |
| host_op_rate 85866 |
| host_tick_rate 519360115 |
| host_mem_usage 279788 |
| host_seconds 0.06 |
| sim_insts 4605 |
| sim_ops 5391 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.physmem.bytes_read::cpu.inst 19456 |
| system.physmem.bytes_read::cpu.data 7424 |
| system.physmem.bytes_read::total 26880 |
| system.physmem.bytes_inst_read::cpu.inst 19456 |
| system.physmem.bytes_inst_read::total 19456 |
| system.physmem.num_reads::cpu.inst 304 |
| system.physmem.num_reads::cpu.data 116 |
| system.physmem.num_reads::total 420 |
| system.physmem.bw_read::cpu.inst 596489614 |
| system.physmem.bw_read::cpu.data 227607879 |
| system.physmem.bw_read::total 824097494 |
| system.physmem.bw_inst_read::cpu.inst 596489614 |
| system.physmem.bw_inst_read::total 596489614 |
| system.physmem.bw_total::cpu.inst 596489614 |
| system.physmem.bw_total::cpu.data 227607879 |
| system.physmem.bw_total::total 824097494 |
| system.physmem.readReqs 420 |
| system.physmem.writeReqs 0 |
| system.physmem.readBursts 420 |
| system.physmem.writeBursts 0 |
| system.physmem.bytesReadDRAM 26880 |
| system.physmem.bytesReadWrQ 0 |
| system.physmem.bytesWritten 0 |
| system.physmem.bytesReadSys 26880 |
| system.physmem.bytesWrittenSys 0 |
| system.physmem.servicedByWrQ 0 |
| system.physmem.mergedWrBursts 0 |
| system.physmem.neitherReadNorWriteReqs 0 |
| system.physmem.perBankRdBursts::0 91 |
| system.physmem.perBankRdBursts::1 52 |
| system.physmem.perBankRdBursts::2 20 |
| system.physmem.perBankRdBursts::3 43 |
| system.physmem.perBankRdBursts::4 21 |
| system.physmem.perBankRdBursts::5 41 |
| system.physmem.perBankRdBursts::6 36 |
| system.physmem.perBankRdBursts::7 12 |
| system.physmem.perBankRdBursts::8 5 |
| system.physmem.perBankRdBursts::9 6 |
| system.physmem.perBankRdBursts::10 27 |
| system.physmem.perBankRdBursts::11 42 |
| system.physmem.perBankRdBursts::12 9 |
| system.physmem.perBankRdBursts::13 8 |
| system.physmem.perBankRdBursts::14 0 |
| system.physmem.perBankRdBursts::15 7 |
| system.physmem.perBankWrBursts::0 0 |
| system.physmem.perBankWrBursts::1 0 |
| system.physmem.perBankWrBursts::2 0 |
| system.physmem.perBankWrBursts::3 0 |
| system.physmem.perBankWrBursts::4 0 |
| system.physmem.perBankWrBursts::5 0 |
| system.physmem.perBankWrBursts::6 0 |
| system.physmem.perBankWrBursts::7 0 |
| system.physmem.perBankWrBursts::8 0 |
| system.physmem.perBankWrBursts::9 0 |
| system.physmem.perBankWrBursts::10 0 |
| system.physmem.perBankWrBursts::11 0 |
| system.physmem.perBankWrBursts::12 0 |
| system.physmem.perBankWrBursts::13 0 |
| system.physmem.perBankWrBursts::14 0 |
| system.physmem.perBankWrBursts::15 0 |
| system.physmem.numRdRetry 0 |
| system.physmem.numWrRetry 0 |
| system.physmem.totGap 32519500 |
| system.physmem.readPktSize::0 0 |
| system.physmem.readPktSize::1 0 |
| system.physmem.readPktSize::2 0 |
| system.physmem.readPktSize::3 0 |
| system.physmem.readPktSize::4 0 |
| system.physmem.readPktSize::5 0 |
| system.physmem.readPktSize::6 420 |
| system.physmem.writePktSize::0 0 |
| system.physmem.writePktSize::1 0 |
| system.physmem.writePktSize::2 0 |
| system.physmem.writePktSize::3 0 |
| system.physmem.writePktSize::4 0 |
| system.physmem.writePktSize::5 0 |
| system.physmem.writePktSize::6 0 |
| system.physmem.rdQLenPdf::0 342 |
| system.physmem.rdQLenPdf::1 70 |
| system.physmem.rdQLenPdf::2 8 |
| system.physmem.rdQLenPdf::3 0 |
| system.physmem.rdQLenPdf::4 0 |
| system.physmem.rdQLenPdf::5 0 |
| system.physmem.rdQLenPdf::6 0 |
| system.physmem.rdQLenPdf::7 0 |
| system.physmem.rdQLenPdf::8 0 |
| system.physmem.rdQLenPdf::9 0 |
| system.physmem.rdQLenPdf::10 0 |
| system.physmem.rdQLenPdf::11 0 |
| system.physmem.rdQLenPdf::12 0 |
| system.physmem.rdQLenPdf::13 0 |
| system.physmem.rdQLenPdf::14 0 |
| system.physmem.rdQLenPdf::15 0 |
| system.physmem.rdQLenPdf::16 0 |
| system.physmem.rdQLenPdf::17 0 |
| system.physmem.rdQLenPdf::18 0 |
| system.physmem.rdQLenPdf::19 0 |
| system.physmem.rdQLenPdf::20 0 |
| system.physmem.rdQLenPdf::21 0 |
| system.physmem.rdQLenPdf::22 0 |
| system.physmem.rdQLenPdf::23 0 |
| system.physmem.rdQLenPdf::24 0 |
| system.physmem.rdQLenPdf::25 0 |
| system.physmem.rdQLenPdf::26 0 |
| system.physmem.rdQLenPdf::27 0 |
| system.physmem.rdQLenPdf::28 0 |
| system.physmem.rdQLenPdf::29 0 |
| system.physmem.rdQLenPdf::30 0 |
| system.physmem.rdQLenPdf::31 0 |
| system.physmem.wrQLenPdf::0 0 |
| system.physmem.wrQLenPdf::1 0 |
| system.physmem.wrQLenPdf::2 0 |
| system.physmem.wrQLenPdf::3 0 |
| system.physmem.wrQLenPdf::4 0 |
| system.physmem.wrQLenPdf::5 0 |
| system.physmem.wrQLenPdf::6 0 |
| system.physmem.wrQLenPdf::7 0 |
| system.physmem.wrQLenPdf::8 0 |
| system.physmem.wrQLenPdf::9 0 |
| system.physmem.wrQLenPdf::10 0 |
| system.physmem.wrQLenPdf::11 0 |
| system.physmem.wrQLenPdf::12 0 |
| system.physmem.wrQLenPdf::13 0 |
| system.physmem.wrQLenPdf::14 0 |
| system.physmem.wrQLenPdf::15 0 |
| system.physmem.wrQLenPdf::16 0 |
| system.physmem.wrQLenPdf::17 0 |
| system.physmem.wrQLenPdf::18 0 |
| system.physmem.wrQLenPdf::19 0 |
| system.physmem.wrQLenPdf::20 0 |
| system.physmem.wrQLenPdf::21 0 |
| system.physmem.wrQLenPdf::22 0 |
| system.physmem.wrQLenPdf::23 0 |
| system.physmem.wrQLenPdf::24 0 |
| system.physmem.wrQLenPdf::25 0 |
| system.physmem.wrQLenPdf::26 0 |
| system.physmem.wrQLenPdf::27 0 |
| system.physmem.wrQLenPdf::28 0 |
| system.physmem.wrQLenPdf::29 0 |
| system.physmem.wrQLenPdf::30 0 |
| system.physmem.wrQLenPdf::31 0 |
| system.physmem.wrQLenPdf::32 0 |
| system.physmem.wrQLenPdf::33 0 |
| system.physmem.wrQLenPdf::34 0 |
| system.physmem.wrQLenPdf::35 0 |
| system.physmem.wrQLenPdf::36 0 |
| system.physmem.wrQLenPdf::37 0 |
| system.physmem.wrQLenPdf::38 0 |
| system.physmem.wrQLenPdf::39 0 |
| system.physmem.wrQLenPdf::40 0 |
| system.physmem.wrQLenPdf::41 0 |
| system.physmem.wrQLenPdf::42 0 |
| system.physmem.wrQLenPdf::43 0 |
| system.physmem.wrQLenPdf::44 0 |
| system.physmem.wrQLenPdf::45 0 |
| system.physmem.wrQLenPdf::46 0 |
| system.physmem.wrQLenPdf::47 0 |
| system.physmem.wrQLenPdf::48 0 |
| system.physmem.wrQLenPdf::49 0 |
| system.physmem.wrQLenPdf::50 0 |
| system.physmem.wrQLenPdf::51 0 |
| system.physmem.wrQLenPdf::52 0 |
| system.physmem.wrQLenPdf::53 0 |
| system.physmem.wrQLenPdf::54 0 |
| system.physmem.wrQLenPdf::55 0 |
| system.physmem.wrQLenPdf::56 0 |
| system.physmem.wrQLenPdf::57 0 |
| system.physmem.wrQLenPdf::58 0 |
| system.physmem.wrQLenPdf::59 0 |
| system.physmem.wrQLenPdf::60 0 |
| system.physmem.wrQLenPdf::61 0 |
| system.physmem.wrQLenPdf::62 0 |
| system.physmem.wrQLenPdf::63 0 |
| system.physmem.bytesPerActivate::samples 70 |
| system.physmem.bytesPerActivate::mean 373.942857 |
| system.physmem.bytesPerActivate::gmean 254.068407 |
| system.physmem.bytesPerActivate::stdev 318.910277 |
| system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% |
| system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% |
| system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% |
| system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% |
| system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% |
| system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% |
| system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% |
| system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% |
| system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% |
| system.physmem.bytesPerActivate::total 70 |
| system.physmem.totQLat 5148000 |
| system.physmem.totMemAccLat 13023000 |
| system.physmem.totBusLat 2100000 |
| system.physmem.avgQLat 12257.14 |
| system.physmem.avgBusLat 5000.00 |
| system.physmem.avgMemAccLat 31007.14 |
| system.physmem.avgRdBW 824.10 |
| system.physmem.avgWrBW 0.00 |
| system.physmem.avgRdBWSys 824.10 |
| system.physmem.avgWrBWSys 0.00 |
| system.physmem.peakBW 12800.00 |
| system.physmem.busUtil 6.44 |
| system.physmem.busUtilRead 6.44 |
| system.physmem.busUtilWrite 0.00 |
| system.physmem.avgRdQLen 1.23 |
| system.physmem.avgWrQLen 0.00 |
| system.physmem.readRowHits 346 |
| system.physmem.writeRowHits 0 |
| system.physmem.readRowHitRate 82.38 |
| system.physmem.writeRowHitRate nan |
| system.physmem.avgGap 77427.38 |
| system.physmem.pageHitRate 82.38 |
| system.physmem_0.actEnergy 349860 |
| system.physmem_0.preEnergy 174570 |
| system.physmem_0.readEnergy 2256240 |
| system.physmem_0.writeEnergy 0 |
| system.physmem_0.refreshEnergy 2458560.000000 |
| system.physmem_0.actBackEnergy 4399260 |
| system.physmem_0.preBackEnergy 59520 |
| system.physmem_0.actPowerDownEnergy 10401930 |
| system.physmem_0.prePowerDownEnergy 1440 |
| system.physmem_0.selfRefreshEnergy 0 |
| system.physmem_0.totalEnergy 20101380 |
| system.physmem_0.averagePower 616.275926 |
| system.physmem_0.totalIdleTime 22764750 |
| system.physmem_0.memoryStateTime::IDLE 30000 |
| system.physmem_0.memoryStateTime::REF 1040000 |
| system.physmem_0.memoryStateTime::SREF 0 |
| system.physmem_0.memoryStateTime::PRE_PDN 3750 |
| system.physmem_0.memoryStateTime::ACT 8725000 |
| system.physmem_0.memoryStateTime::ACT_PDN 22818750 |
| system.physmem_1.actEnergy 178500 |
| system.physmem_1.preEnergy 91080 |
| system.physmem_1.readEnergy 742560 |
| system.physmem_1.writeEnergy 0 |
| system.physmem_1.refreshEnergy 2458560.000000 |
| system.physmem_1.actBackEnergy 1740780 |
| system.physmem_1.preBackEnergy 96960 |
| system.physmem_1.actPowerDownEnergy 12060060 |
| system.physmem_1.prePowerDownEnergy 806400 |
| system.physmem_1.selfRefreshEnergy 0 |
| system.physmem_1.totalEnergy 18174900 |
| system.physmem_1.averagePower 557.213152 |
| system.physmem_1.totalIdleTime 28278000 |
| system.physmem_1.memoryStateTime::IDLE 141000 |
| system.physmem_1.memoryStateTime::REF 1040000 |
| system.physmem_1.memoryStateTime::SREF 0 |
| system.physmem_1.memoryStateTime::PRE_PDN 2099750 |
| system.physmem_1.memoryStateTime::ACT 2887500 |
| system.physmem_1.memoryStateTime::ACT_PDN 26449250 |
| system.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.branchPred.lookups 1965 |
| system.cpu.branchPred.condPredicted 1175 |
| system.cpu.branchPred.condIncorrect 349 |
| system.cpu.branchPred.BTBLookups 1668 |
| system.cpu.branchPred.BTBHits 324 |
| system.cpu.branchPred.BTBCorrect 0 |
| system.cpu.branchPred.BTBHitPct 19.424460 |
| system.cpu.branchPred.usedRAS 220 |
| system.cpu.branchPred.RASInCorrect 16 |
| system.cpu.branchPred.indirectLookups 137 |
| system.cpu.branchPred.indirectHits 8 |
| system.cpu.branchPred.indirectMisses 129 |
| system.cpu.branchPredindirectMispredicted 63 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 13 |
| system.cpu.pwrStateResidencyTicks::ON 32617500 |
| system.cpu.numCycles 65235 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 4605 |
| system.cpu.committedOps 5391 |
| system.cpu.discardedOps 1187 |
| system.cpu.numFetchSuspends 0 |
| system.cpu.cpi 14.166124 |
| system.cpu.ipc 0.070591 |
| system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% |
| system.cpu.op_class_0::IntMult 4 0.07% 63.49% |
| system.cpu.op_class_0::IntDiv 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatMult 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% |
| system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdMult 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdShift 0 0.00% 63.49% |
| system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% |
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| system.cpu.l2cache.overall_mshr_misses::total 420 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 471 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 424 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 4 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 43 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 43 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 |
| system.cpu.toL2Bus.pkt_count::total 938 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 |
| system.cpu.toL2Bus.pkt_size::total 30144 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 467 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.100642 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% |
| system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 467 |
| system.cpu.toL2Bus.reqLayer0.occupancy 239500 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.7 |
| system.cpu.toL2Bus.respLayer0.occupancy 481500 |
| system.cpu.toL2Bus.respLayer0.utilization 1.5 |
| system.cpu.toL2Bus.respLayer1.occupancy 222992 |
| system.cpu.toL2Bus.respLayer1.utilization 0.7 |
| system.membus.snoop_filter.tot_requests 420 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 |
| system.membus.trans_dist::ReadResp 377 |
| system.membus.trans_dist::ReadExReq 43 |
| system.membus.trans_dist::ReadExResp 43 |
| system.membus.trans_dist::ReadSharedReq 377 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 |
| system.membus.pkt_count::total 840 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 |
| system.membus.pkt_size::total 26880 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 420 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 420 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 420 |
| system.membus.reqLayer0.occupancy 489000 |
| system.membus.reqLayer0.utilization 1.5 |
| system.membus.respLayer1.occupancy 2233000 |
| system.membus.respLayer1.utilization 6.8 |
| |
| ---------- End Simulation Statistics ---------- |
