| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| exit_on_work_items=false |
| init_param=0 |
| kernel= |
| kernel_addr_check=true |
| load_addr_mask=1099511627775 |
| load_offset=0 |
| mem_mode=atomic |
| mem_ranges= |
| memories=system.physmem |
| mmap_using_noreserve=false |
| multi_thread=false |
| num_work_ids=16 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| readfile= |
| symbolfile= |
| thermal_components= |
| thermal_model=Null |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[0] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| clock=1000 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.cpu] |
| type=AtomicSimpleCPU |
| children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload |
| branchPred=Null |
| checker=system.cpu.checker |
| clk_domain=system.cpu_clk_domain |
| cpu_id=0 |
| default_p_state=UNDEFINED |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dstage2_mmu=system.cpu.dstage2_mmu |
| dtb=system.cpu.dtb |
| eventq_index=0 |
| fastmem=false |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu.interrupts |
| isa=system.cpu.isa |
| istage2_mmu=system.cpu.istage2_mmu |
| itb=system.cpu.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| profile=0 |
| progress_interval=0 |
| simpoint_start_insts= |
| simulate_data_stalls=false |
| simulate_inst_stalls=false |
| socket_id=0 |
| switched_out=false |
| syscallRetryLatency=10000 |
| system=system |
| tracer=system.cpu.tracer |
| width=1 |
| workload=system.cpu.workload |
| dcache_port=system.membus.slave[2] |
| icache_port=system.membus.slave[1] |
| |
| [system.cpu.checker] |
| type=DummyChecker |
| children=dstage2_mmu dtb isa istage2_mmu itb tracer |
| checker=Null |
| clk_domain=system.cpu_clk_domain |
| cpu_id=-1 |
| default_p_state=UNDEFINED |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dstage2_mmu=system.cpu.checker.dstage2_mmu |
| dtb=system.cpu.checker.dtb |
| eventq_index=0 |
| exitOnError=false |
| function_trace=false |
| function_trace_start=0 |
| interrupts= |
| isa=system.cpu.checker.isa |
| istage2_mmu=system.cpu.checker.istage2_mmu |
| itb=system.cpu.checker.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| profile=0 |
| progress_interval=0 |
| simpoint_start_insts= |
| socket_id=0 |
| switched_out=false |
| syscallRetryLatency=10000 |
| system=system |
| tracer=system.cpu.checker.tracer |
| updateOnError=false |
| warnOnlyOnLoadError=true |
| workload=system.cpu.workload |
| |
| [system.cpu.checker.dstage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.checker.dtb |
| |
| [system.cpu.checker.dstage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.checker.dstage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.checker.dtb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.checker.dtb.walker |
| |
| [system.cpu.checker.dtb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.checker.isa] |
| type=ArmISA |
| decoderFlavour=Generic |
| eventq_index=0 |
| fpsid=1090793632 |
| id_aa64afr0_el1=0 |
| id_aa64afr1_el1=0 |
| id_aa64dfr0_el1=1052678 |
| id_aa64dfr1_el1=0 |
| id_aa64isar0_el1=0 |
| id_aa64isar1_el1=0 |
| id_aa64mmfr0_el1=15728642 |
| id_aa64mmfr1_el1=0 |
| id_isar0=34607377 |
| id_isar1=34677009 |
| id_isar2=555950401 |
| id_isar3=17899825 |
| id_isar4=268501314 |
| id_isar5=0 |
| id_mmfr0=270536963 |
| id_mmfr1=0 |
| id_mmfr2=19070976 |
| id_mmfr3=34611729 |
| midr=1091551472 |
| pmu=Null |
| system=system |
| |
| [system.cpu.checker.istage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.checker.itb |
| |
| [system.cpu.checker.istage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.checker.istage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.checker.itb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.checker.itb.walker |
| |
| [system.cpu.checker.itb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.checker.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.dstage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.dtb |
| |
| [system.cpu.dstage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.dstage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.dstage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.dtb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.dtb.walker |
| |
| [system.cpu.dtb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.membus.slave[4] |
| |
| [system.cpu.interrupts] |
| type=ArmInterrupts |
| eventq_index=0 |
| |
| [system.cpu.isa] |
| type=ArmISA |
| decoderFlavour=Generic |
| eventq_index=0 |
| fpsid=1090793632 |
| id_aa64afr0_el1=0 |
| id_aa64afr1_el1=0 |
| id_aa64dfr0_el1=1052678 |
| id_aa64dfr1_el1=0 |
| id_aa64isar0_el1=0 |
| id_aa64isar1_el1=0 |
| id_aa64mmfr0_el1=15728642 |
| id_aa64mmfr1_el1=0 |
| id_isar0=34607377 |
| id_isar1=34677009 |
| id_isar2=555950401 |
| id_isar3=17899825 |
| id_isar4=268501314 |
| id_isar5=0 |
| id_mmfr0=270536963 |
| id_mmfr1=0 |
| id_mmfr2=19070976 |
| id_mmfr3=34611729 |
| midr=1091551472 |
| pmu=Null |
| system=system |
| |
| [system.cpu.istage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.itb |
| |
| [system.cpu.istage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.istage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.istage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.itb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.itb.walker |
| |
| [system.cpu.itb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.membus.slave[3] |
| |
| [system.cpu.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.workload] |
| type=Process |
| cmd=hello |
| cwd= |
| drivers= |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| eventq_index=0 |
| executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello |
| gid=100 |
| input=cin |
| kvmInSE=false |
| maxStackSize=67108864 |
| output=cout |
| pgid=100 |
| pid=100 |
| ppid=0 |
| simpoint=0 |
| system=system |
| uid=100 |
| useArchPT=false |
| |
| [system.cpu_clk_domain] |
| type=SrcClockDomain |
| clock=500 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.dvfs_handler] |
| type=DVFSHandler |
| domains= |
| enable=false |
| eventq_index=0 |
| sys_clk_domain=system.clk_domain |
| transition_latency=100000000 |
| |
| [system.membus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=4 |
| frontend_latency=3 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=true |
| power_model=Null |
| response_latency=2 |
| snoop_filter=system.membus.snoop_filter |
| snoop_response_latency=4 |
| system=system |
| use_default_range=false |
| width=16 |
| master=system.physmem.port |
| slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| |
| [system.membus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=1 |
| max_capacity=8388608 |
| system=system |
| |
| [system.physmem] |
| type=SimpleMemory |
| bandwidth=73.000000 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| in_addr_map=true |
| kvm_map=true |
| latency=30000 |
| latency_var=0 |
| null=false |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| range=0:134217727:0:0:0:0 |
| port=system.membus.master[0] |
| |
| [system.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
