| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000022 |
| sim_ticks 22347000 |
| final_tick 22347000 |
| sim_freq 1000000000000 |
| host_inst_rate 10860 |
| host_op_rate 10877 |
| host_tick_rate 43710468 |
| host_mem_usage 261260 |
| host_seconds 0.51 |
| sim_insts 5552 |
| sim_ops 5561 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.physmem.bytes_read::cpu.inst 19776 |
| system.physmem.bytes_read::cpu.data 9344 |
| system.physmem.bytes_read::total 29120 |
| system.physmem.bytes_inst_read::cpu.inst 19776 |
| system.physmem.bytes_inst_read::total 19776 |
| system.physmem.num_reads::cpu.inst 309 |
| system.physmem.num_reads::cpu.data 146 |
| system.physmem.num_reads::total 455 |
| system.physmem.bw_read::cpu.inst 884951000 |
| system.physmem.bw_read::cpu.data 418132188 |
| system.physmem.bw_read::total 1303083188 |
| system.physmem.bw_inst_read::cpu.inst 884951000 |
| system.physmem.bw_inst_read::total 884951000 |
| system.physmem.bw_total::cpu.inst 884951000 |
| system.physmem.bw_total::cpu.data 418132188 |
| system.physmem.bw_total::total 1303083188 |
| system.physmem.readReqs 455 |
| system.physmem.writeReqs 0 |
| system.physmem.readBursts 455 |
| system.physmem.writeBursts 0 |
| system.physmem.bytesReadDRAM 29120 |
| system.physmem.bytesReadWrQ 0 |
| system.physmem.bytesWritten 0 |
| system.physmem.bytesReadSys 29120 |
| system.physmem.bytesWrittenSys 0 |
| system.physmem.servicedByWrQ 0 |
| system.physmem.mergedWrBursts 0 |
| system.physmem.neitherReadNorWriteReqs 0 |
| system.physmem.perBankRdBursts::0 32 |
| system.physmem.perBankRdBursts::1 0 |
| system.physmem.perBankRdBursts::2 32 |
| system.physmem.perBankRdBursts::3 19 |
| system.physmem.perBankRdBursts::4 64 |
| system.physmem.perBankRdBursts::5 93 |
| system.physmem.perBankRdBursts::6 68 |
| system.physmem.perBankRdBursts::7 54 |
| system.physmem.perBankRdBursts::8 56 |
| system.physmem.perBankRdBursts::9 30 |
| system.physmem.perBankRdBursts::10 0 |
| system.physmem.perBankRdBursts::11 2 |
| system.physmem.perBankRdBursts::12 2 |
| system.physmem.perBankRdBursts::13 2 |
| system.physmem.perBankRdBursts::14 1 |
| system.physmem.perBankRdBursts::15 0 |
| system.physmem.perBankWrBursts::0 0 |
| system.physmem.perBankWrBursts::1 0 |
| system.physmem.perBankWrBursts::2 0 |
| system.physmem.perBankWrBursts::3 0 |
| system.physmem.perBankWrBursts::4 0 |
| system.physmem.perBankWrBursts::5 0 |
| system.physmem.perBankWrBursts::6 0 |
| system.physmem.perBankWrBursts::7 0 |
| system.physmem.perBankWrBursts::8 0 |
| system.physmem.perBankWrBursts::9 0 |
| system.physmem.perBankWrBursts::10 0 |
| system.physmem.perBankWrBursts::11 0 |
| system.physmem.perBankWrBursts::12 0 |
| system.physmem.perBankWrBursts::13 0 |
| system.physmem.perBankWrBursts::14 0 |
| system.physmem.perBankWrBursts::15 0 |
| system.physmem.numRdRetry 0 |
| system.physmem.numWrRetry 0 |
| system.physmem.totGap 22262000 |
| system.physmem.readPktSize::0 0 |
| system.physmem.readPktSize::1 0 |
| system.physmem.readPktSize::2 0 |
| system.physmem.readPktSize::3 0 |
| system.physmem.readPktSize::4 0 |
| system.physmem.readPktSize::5 0 |
| system.physmem.readPktSize::6 455 |
| system.physmem.writePktSize::0 0 |
| system.physmem.writePktSize::1 0 |
| system.physmem.writePktSize::2 0 |
| system.physmem.writePktSize::3 0 |
| system.physmem.writePktSize::4 0 |
| system.physmem.writePktSize::5 0 |
| system.physmem.writePktSize::6 0 |
| system.physmem.rdQLenPdf::0 236 |
| system.physmem.rdQLenPdf::1 133 |
| system.physmem.rdQLenPdf::2 60 |
| system.physmem.rdQLenPdf::3 17 |
| system.physmem.rdQLenPdf::4 6 |
| system.physmem.rdQLenPdf::5 3 |
| system.physmem.rdQLenPdf::6 0 |
| system.physmem.rdQLenPdf::7 0 |
| system.physmem.rdQLenPdf::8 0 |
| system.physmem.rdQLenPdf::9 0 |
| system.physmem.rdQLenPdf::10 0 |
| system.physmem.rdQLenPdf::11 0 |
| system.physmem.rdQLenPdf::12 0 |
| system.physmem.rdQLenPdf::13 0 |
| system.physmem.rdQLenPdf::14 0 |
| system.physmem.rdQLenPdf::15 0 |
| system.physmem.rdQLenPdf::16 0 |
| system.physmem.rdQLenPdf::17 0 |
| system.physmem.rdQLenPdf::18 0 |
| system.physmem.rdQLenPdf::19 0 |
| system.physmem.rdQLenPdf::20 0 |
| system.physmem.rdQLenPdf::21 0 |
| system.physmem.rdQLenPdf::22 0 |
| system.physmem.rdQLenPdf::23 0 |
| system.physmem.rdQLenPdf::24 0 |
| system.physmem.rdQLenPdf::25 0 |
| system.physmem.rdQLenPdf::26 0 |
| system.physmem.rdQLenPdf::27 0 |
| system.physmem.rdQLenPdf::28 0 |
| system.physmem.rdQLenPdf::29 0 |
| system.physmem.rdQLenPdf::30 0 |
| system.physmem.rdQLenPdf::31 0 |
| system.physmem.wrQLenPdf::0 0 |
| system.physmem.wrQLenPdf::1 0 |
| system.physmem.wrQLenPdf::2 0 |
| system.physmem.wrQLenPdf::3 0 |
| system.physmem.wrQLenPdf::4 0 |
| system.physmem.wrQLenPdf::5 0 |
| system.physmem.wrQLenPdf::6 0 |
| system.physmem.wrQLenPdf::7 0 |
| system.physmem.wrQLenPdf::8 0 |
| system.physmem.wrQLenPdf::9 0 |
| system.physmem.wrQLenPdf::10 0 |
| system.physmem.wrQLenPdf::11 0 |
| system.physmem.wrQLenPdf::12 0 |
| system.physmem.wrQLenPdf::13 0 |
| system.physmem.wrQLenPdf::14 0 |
| system.physmem.wrQLenPdf::15 0 |
| system.physmem.wrQLenPdf::16 0 |
| system.physmem.wrQLenPdf::17 0 |
| system.physmem.wrQLenPdf::18 0 |
| system.physmem.wrQLenPdf::19 0 |
| system.physmem.wrQLenPdf::20 0 |
| system.physmem.wrQLenPdf::21 0 |
| system.physmem.wrQLenPdf::22 0 |
| system.physmem.wrQLenPdf::23 0 |
| system.physmem.wrQLenPdf::24 0 |
| system.physmem.wrQLenPdf::25 0 |
| system.physmem.wrQLenPdf::26 0 |
| system.physmem.wrQLenPdf::27 0 |
| system.physmem.wrQLenPdf::28 0 |
| system.physmem.wrQLenPdf::29 0 |
| system.physmem.wrQLenPdf::30 0 |
| system.physmem.wrQLenPdf::31 0 |
| system.physmem.wrQLenPdf::32 0 |
| system.physmem.wrQLenPdf::33 0 |
| system.physmem.wrQLenPdf::34 0 |
| system.physmem.wrQLenPdf::35 0 |
| system.physmem.wrQLenPdf::36 0 |
| system.physmem.wrQLenPdf::37 0 |
| system.physmem.wrQLenPdf::38 0 |
| system.physmem.wrQLenPdf::39 0 |
| system.physmem.wrQLenPdf::40 0 |
| system.physmem.wrQLenPdf::41 0 |
| system.physmem.wrQLenPdf::42 0 |
| system.physmem.wrQLenPdf::43 0 |
| system.physmem.wrQLenPdf::44 0 |
| system.physmem.wrQLenPdf::45 0 |
| system.physmem.wrQLenPdf::46 0 |
| system.physmem.wrQLenPdf::47 0 |
| system.physmem.wrQLenPdf::48 0 |
| system.physmem.wrQLenPdf::49 0 |
| system.physmem.wrQLenPdf::50 0 |
| system.physmem.wrQLenPdf::51 0 |
| system.physmem.wrQLenPdf::52 0 |
| system.physmem.wrQLenPdf::53 0 |
| system.physmem.wrQLenPdf::54 0 |
| system.physmem.wrQLenPdf::55 0 |
| system.physmem.wrQLenPdf::56 0 |
| system.physmem.wrQLenPdf::57 0 |
| system.physmem.wrQLenPdf::58 0 |
| system.physmem.wrQLenPdf::59 0 |
| system.physmem.wrQLenPdf::60 0 |
| system.physmem.wrQLenPdf::61 0 |
| system.physmem.wrQLenPdf::62 0 |
| system.physmem.wrQLenPdf::63 0 |
| system.physmem.bytesPerActivate::samples 100 |
| system.physmem.bytesPerActivate::mean 271.360000 |
| system.physmem.bytesPerActivate::gmean 169.923942 |
| system.physmem.bytesPerActivate::stdev 289.967867 |
| system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% |
| system.physmem.bytesPerActivate::128-255 30 30.00% 65.00% |
| system.physmem.bytesPerActivate::256-383 11 11.00% 76.00% |
| system.physmem.bytesPerActivate::384-511 6 6.00% 82.00% |
| system.physmem.bytesPerActivate::512-639 4 4.00% 86.00% |
| system.physmem.bytesPerActivate::640-767 3 3.00% 89.00% |
| system.physmem.bytesPerActivate::768-895 2 2.00% 91.00% |
| system.physmem.bytesPerActivate::896-1023 2 2.00% 93.00% |
| system.physmem.bytesPerActivate::1024-1151 7 7.00% 100.00% |
| system.physmem.bytesPerActivate::total 100 |
| system.physmem.totQLat 7985750 |
| system.physmem.totMemAccLat 16517000 |
| system.physmem.totBusLat 2275000 |
| system.physmem.avgQLat 17551.10 |
| system.physmem.avgBusLat 5000.00 |
| system.physmem.avgMemAccLat 36301.10 |
| system.physmem.avgRdBW 1303.08 |
| system.physmem.avgWrBW 0.00 |
| system.physmem.avgRdBWSys 1303.08 |
| system.physmem.avgWrBWSys 0.00 |
| system.physmem.peakBW 12800.00 |
| system.physmem.busUtil 10.18 |
| system.physmem.busUtilRead 10.18 |
| system.physmem.busUtilWrite 0.00 |
| system.physmem.avgRdQLen 1.85 |
| system.physmem.avgWrQLen 0.00 |
| system.physmem.readRowHits 345 |
| system.physmem.writeRowHits 0 |
| system.physmem.readRowHitRate 75.82 |
| system.physmem.writeRowHitRate nan |
| system.physmem.avgGap 48927.47 |
| system.physmem.pageHitRate 75.82 |
| system.physmem_0.actEnergy 628320 |
| system.physmem_0.preEnergy 307395 |
| system.physmem_0.readEnergy 2584680 |
| system.physmem_0.writeEnergy 0 |
| system.physmem_0.refreshEnergy 1229280.000000 |
| system.physmem_0.actBackEnergy 4082340 |
| system.physmem_0.preBackEnergy 28320 |
| system.physmem_0.actPowerDownEnergy 6073920 |
| system.physmem_0.prePowerDownEnergy 480 |
| system.physmem_0.selfRefreshEnergy 0 |
| system.physmem_0.totalEnergy 14934735 |
| system.physmem_0.averagePower 668.295559 |
| system.physmem_0.totalIdleTime 13169250 |
| system.physmem_0.memoryStateTime::IDLE 17500 |
| system.physmem_0.memoryStateTime::REF 520000 |
| system.physmem_0.memoryStateTime::SREF 0 |
| system.physmem_0.memoryStateTime::PRE_PDN 1250 |
| system.physmem_0.memoryStateTime::ACT 8498250 |
| system.physmem_0.memoryStateTime::ACT_PDN 13310000 |
| system.physmem_1.actEnergy 157080 |
| system.physmem_1.preEnergy 72105 |
| system.physmem_1.readEnergy 664020 |
| system.physmem_1.writeEnergy 0 |
| system.physmem_1.refreshEnergy 1229280.000000 |
| system.physmem_1.actBackEnergy 1349190 |
| system.physmem_1.preBackEnergy 207840 |
| system.physmem_1.actPowerDownEnergy 8004510 |
| system.physmem_1.prePowerDownEnergy 496800 |
| system.physmem_1.selfRefreshEnergy 0 |
| system.physmem_1.totalEnergy 12180825 |
| system.physmem_1.averagePower 545.064325 |
| system.physmem_1.totalIdleTime 18795500 |
| system.physmem_1.memoryStateTime::IDLE 472250 |
| system.physmem_1.memoryStateTime::REF 520000 |
| system.physmem_1.memoryStateTime::SREF 0 |
| system.physmem_1.memoryStateTime::PRE_PDN 1293000 |
| system.physmem_1.memoryStateTime::ACT 2510500 |
| system.physmem_1.memoryStateTime::ACT_PDN 17551250 |
| system.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.branchPred.lookups 2633 |
| system.cpu.branchPred.condPredicted 1922 |
| system.cpu.branchPred.condIncorrect 704 |
| system.cpu.branchPred.BTBLookups 2323 |
| system.cpu.branchPred.BTBHits 541 |
| system.cpu.branchPred.BTBCorrect 0 |
| system.cpu.branchPred.BTBHitPct 23.288851 |
| system.cpu.branchPred.usedRAS 0 |
| system.cpu.branchPred.RASInCorrect 0 |
| system.cpu.branchPred.indirectLookups 470 |
| system.cpu.branchPred.indirectHits 45 |
| system.cpu.branchPred.indirectMisses 425 |
| system.cpu.branchPredindirectMispredicted 203 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 9 |
| system.cpu.pwrStateResidencyTicks::ON 22347000 |
| system.cpu.numCycles 44695 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.fetch.icacheStallCycles 7412 |
| system.cpu.fetch.Insts 11116 |
| system.cpu.fetch.Branches 2633 |
| system.cpu.fetch.predictedBranches 586 |
| system.cpu.fetch.Cycles 8264 |
| system.cpu.fetch.SquashCycles 1434 |
| system.cpu.fetch.MiscStallCycles 3 |
| system.cpu.fetch.IcacheWaitRetryStallCycles 53 |
| system.cpu.fetch.CacheLines 1371 |
| system.cpu.fetch.IcacheSquashes 238 |
| system.cpu.fetch.rateDist::samples 16449 |
| system.cpu.fetch.rateDist::mean 0.677062 |
| system.cpu.fetch.rateDist::stdev 1.083698 |
| system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu.fetch.rateDist::0 9314 56.62% 56.62% |
| system.cpu.fetch.rateDist::1 5053 30.72% 87.34% |
| system.cpu.fetch.rateDist::2 1133 6.89% 94.23% |
| system.cpu.fetch.rateDist::3 492 2.99% 97.22% |
| system.cpu.fetch.rateDist::4 212 1.29% 98.51% |
| system.cpu.fetch.rateDist::5 105 0.64% 99.15% |
| system.cpu.fetch.rateDist::6 66 0.40% 99.55% |
| system.cpu.fetch.rateDist::7 19 0.12% 99.67% |
| system.cpu.fetch.rateDist::8 55 0.33% 100.00% |
| system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu.fetch.rateDist::min_value 0 |
| system.cpu.fetch.rateDist::max_value 8 |
| system.cpu.fetch.rateDist::total 16449 |
| system.cpu.fetch.branchRate 0.058910 |
| system.cpu.fetch.rate 0.248708 |
| system.cpu.decode.IdleCycles 6659 |
| system.cpu.decode.BlockedCycles 3259 |
| system.cpu.decode.RunCycles 5898 |
| system.cpu.decode.UnblockCycles 97 |
| system.cpu.decode.SquashCycles 536 |
| system.cpu.decode.BranchResolved 583 |
| system.cpu.decode.BranchMispred 193 |
| system.cpu.decode.DecodedInsts 9866 |
| system.cpu.decode.SquashedInsts 251 |
| system.cpu.rename.SquashCycles 536 |
| system.cpu.rename.IdleCycles 7139 |
| system.cpu.rename.BlockCycles 517 |
| system.cpu.rename.serializeStallCycles 1672 |
| system.cpu.rename.RunCycles 5505 |
| system.cpu.rename.UnblockCycles 1080 |
| system.cpu.rename.RenamedInsts 9269 |
| system.cpu.rename.IQFullEvents 3 |
| system.cpu.rename.SQFullEvents 1060 |
| system.cpu.rename.RenamedOperands 5973 |
| system.cpu.rename.RenameLookups 11207 |
| system.cpu.rename.int_rename_lookups 11195 |
| system.cpu.rename.fp_rename_lookups 12 |
| system.cpu.rename.CommittedMaps 3414 |
| system.cpu.rename.UndoneMaps 2559 |
| system.cpu.rename.serializingInsts 30 |
| system.cpu.rename.tempSerializingInsts 30 |
| system.cpu.rename.skidInsts 310 |
| system.cpu.memDep0.insertedLoads 1637 |
| system.cpu.memDep0.insertedStores 1317 |
| system.cpu.memDep0.conflictingLoads 6 |
| system.cpu.memDep0.conflictingStores 1 |
| system.cpu.iq.iqInstsAdded 8273 |
| system.cpu.iq.iqNonSpecInstsAdded 44 |
| system.cpu.iq.iqInstsIssued 7695 |
| system.cpu.iq.iqSquashedInstsIssued 46 |
| system.cpu.iq.iqSquashedInstsExamined 2754 |
| system.cpu.iq.iqSquashedOperandsExamined 1297 |
| system.cpu.iq.iqSquashedNonSpecRemoved 16 |
| system.cpu.iq.issued_per_cycle::samples 16449 |
| system.cpu.iq.issued_per_cycle::mean 0.467810 |
| system.cpu.iq.issued_per_cycle::stdev 0.872432 |
| system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.iq.issued_per_cycle::0 11408 69.35% 69.35% |
| system.cpu.iq.issued_per_cycle::1 3326 20.22% 89.57% |
| system.cpu.iq.issued_per_cycle::2 1145 6.96% 96.53% |
| system.cpu.iq.issued_per_cycle::3 340 2.07% 98.60% |
| system.cpu.iq.issued_per_cycle::4 157 0.95% 99.56% |
| system.cpu.iq.issued_per_cycle::5 38 0.23% 99.79% |
| system.cpu.iq.issued_per_cycle::6 18 0.11% 99.90% |
| system.cpu.iq.issued_per_cycle::7 3 0.02% 99.91% |
| system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% |
| system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::min_value 0 |
| system.cpu.iq.issued_per_cycle::max_value 8 |
| system.cpu.iq.issued_per_cycle::total 16449 |
| system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu.iq.fu_full::IntAlu 6 27.27% 27.27% |
| system.cpu.iq.fu_full::IntMult 0 0.00% 27.27% |
| system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatMisc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% |
| system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% |
| system.cpu.iq.fu_full::MemRead 6 27.27% 54.55% |
| system.cpu.iq.fu_full::MemWrite 8 36.36% 90.91% |
| system.cpu.iq.fu_full::FloatMemRead 0 0.00% 90.91% |
| system.cpu.iq.fu_full::FloatMemWrite 2 9.09% 100.00% |
| system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::No_OpClass 10 0.13% 0.13% |
| system.cpu.iq.FU_type_0::IntAlu 4809 62.50% 62.63% |
| system.cpu.iq.FU_type_0::IntMult 3 0.04% 62.66% |
| system.cpu.iq.FU_type_0::IntDiv 6 0.08% 62.74% |
| system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% |
| system.cpu.iq.FU_type_0::MemRead 1600 20.79% 83.53% |
| system.cpu.iq.FU_type_0::MemWrite 1255 16.31% 99.84% |
| system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.84% |
| system.cpu.iq.FU_type_0::FloatMemWrite 12 0.16% 100.00% |
| system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::total 7695 |
| system.cpu.iq.rate 0.172167 |
| system.cpu.iq.fu_busy_cnt 22 |
| system.cpu.iq.fu_busy_rate 0.002859 |
| system.cpu.iq.int_inst_queue_reads 31881 |
| system.cpu.iq.int_inst_queue_writes 11063 |
| system.cpu.iq.int_inst_queue_wakeup_accesses 6953 |
| system.cpu.iq.fp_inst_queue_reads 26 |
| system.cpu.iq.fp_inst_queue_writes 12 |
| system.cpu.iq.fp_inst_queue_wakeup_accesses 12 |
| system.cpu.iq.int_alu_accesses 7693 |
| system.cpu.iq.fp_alu_accesses 14 |
| system.cpu.iew.lsq.thread0.forwLoads 12 |
| system.cpu.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu.iew.lsq.thread0.squashedLoads 555 |
| system.cpu.iew.lsq.thread0.ignoredResponses 3 |
| system.cpu.iew.lsq.thread0.memOrderViolation 4 |
| system.cpu.iew.lsq.thread0.squashedStores 237 |
| system.cpu.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu.iew.lsq.thread0.blockedLoads 0 |
| system.cpu.iew.lsq.thread0.rescheduledLoads 0 |
| system.cpu.iew.lsq.thread0.cacheBlocked 44 |
| system.cpu.iew.iewIdleCycles 0 |
| system.cpu.iew.iewSquashCycles 536 |
| system.cpu.iew.iewBlockCycles 495 |
| system.cpu.iew.iewUnblockCycles 23 |
| system.cpu.iew.iewDispatchedInsts 8316 |
| system.cpu.iew.iewDispSquashedInsts 371 |
| system.cpu.iew.iewDispLoadInsts 1637 |
| system.cpu.iew.iewDispStoreInsts 1317 |
| system.cpu.iew.iewDispNonSpecInsts 43 |
| system.cpu.iew.iewIQFullEvents 1 |
| system.cpu.iew.iewLSQFullEvents 18 |
| system.cpu.iew.memOrderViolationEvents 4 |
| system.cpu.iew.predictedTakenIncorrect 84 |
| system.cpu.iew.predictedNotTakenIncorrect 500 |
| system.cpu.iew.branchMispredicts 584 |
| system.cpu.iew.iewExecutedInsts 7197 |
| system.cpu.iew.iewExecLoadInsts 1495 |
| system.cpu.iew.iewExecSquashedInsts 498 |
| system.cpu.iew.exec_swp 0 |
| system.cpu.iew.exec_nop 0 |
| system.cpu.iew.exec_refs 2700 |
| system.cpu.iew.exec_branches 1576 |
| system.cpu.iew.exec_stores 1205 |
| system.cpu.iew.exec_rate 0.161025 |
| system.cpu.iew.wb_sent 7014 |
| system.cpu.iew.wb_count 6965 |
| system.cpu.iew.wb_producers 2327 |
| system.cpu.iew.wb_consumers 3059 |
| system.cpu.iew.wb_rate 0.155834 |
| system.cpu.iew.wb_fanout 0.760706 |
| system.cpu.commit.commitSquashedInsts 2754 |
| system.cpu.commit.commitNonSpecStalls 27 |
| system.cpu.commit.branchMispredicts 523 |
| system.cpu.commit.committed_per_cycle::samples 15734 |
| system.cpu.commit.committed_per_cycle::mean 0.353438 |
| system.cpu.commit.committed_per_cycle::stdev 0.944985 |
| system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.commit.committed_per_cycle::0 12701 80.72% 80.72% |
| system.cpu.commit.committed_per_cycle::1 1816 11.54% 92.27% |
| system.cpu.commit.committed_per_cycle::2 611 3.88% 96.15% |
| system.cpu.commit.committed_per_cycle::3 243 1.54% 97.69% |
| system.cpu.commit.committed_per_cycle::4 211 1.34% 99.03% |
| system.cpu.commit.committed_per_cycle::5 68 0.43% 99.47% |
| system.cpu.commit.committed_per_cycle::6 23 0.15% 99.61% |
| system.cpu.commit.committed_per_cycle::7 16 0.10% 99.71% |
| system.cpu.commit.committed_per_cycle::8 45 0.29% 100.00% |
| system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.commit.committed_per_cycle::min_value 0 |
| system.cpu.commit.committed_per_cycle::max_value 8 |
| system.cpu.commit.committed_per_cycle::total 15734 |
| system.cpu.commit.committedInsts 5552 |
| system.cpu.commit.committedOps 5561 |
| system.cpu.commit.swp_count 0 |
| system.cpu.commit.refs 2162 |
| system.cpu.commit.loads 1082 |
| system.cpu.commit.membars 1 |
| system.cpu.commit.branches 1196 |
| system.cpu.commit.vec_insts 0 |
| system.cpu.commit.fp_insts 12 |
| system.cpu.commit.int_insts 5498 |
| system.cpu.commit.function_calls 282 |
| system.cpu.commit.op_class_0::No_OpClass 1 0.02% 0.02% |
| system.cpu.commit.op_class_0::IntAlu 3392 61.00% 61.01% |
| system.cpu.commit.op_class_0::IntMult 2 0.04% 61.05% |
| system.cpu.commit.op_class_0::IntDiv 4 0.07% 61.12% |
| system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.12% |
| system.cpu.commit.op_class_0::MemRead 1082 19.46% 80.58% |
| system.cpu.commit.op_class_0::MemWrite 1068 19.21% 99.78% |
| system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.78% |
| system.cpu.commit.op_class_0::FloatMemWrite 12 0.22% 100.00% |
| system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu.commit.op_class_0::total 5561 |
| system.cpu.commit.bw_lim_events 45 |
| system.cpu.rob.rob_reads 23900 |
| system.cpu.rob.rob_writes 17354 |
| system.cpu.timesIdled 215 |
| system.cpu.idleCycles 28246 |
| system.cpu.committedInsts 5552 |
| system.cpu.committedOps 5561 |
| system.cpu.cpi 8.050252 |
| system.cpu.cpi_total 8.050252 |
| system.cpu.ipc 0.124220 |
| system.cpu.ipc_total 0.124220 |
| system.cpu.int_regfile_reads 8779 |
| system.cpu.int_regfile_writes 4373 |
| system.cpu.fp_regfile_reads 12 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.dcache.tags.replacements 0 |
| system.cpu.dcache.tags.tagsinuse 89.806285 |
| system.cpu.dcache.tags.total_refs 1992 |
| system.cpu.dcache.tags.sampled_refs 146 |
| system.cpu.dcache.tags.avg_refs 13.643836 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 89.806285 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.021925 |
| system.cpu.dcache.tags.occ_percent::total 0.021925 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 146 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 |
| system.cpu.dcache.tags.tag_accesses 5160 |
| system.cpu.dcache.tags.data_accesses 5160 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.dcache.ReadReq_hits::cpu.data 1284 |
| system.cpu.dcache.ReadReq_hits::total 1284 |
| system.cpu.dcache.WriteReq_hits::cpu.data 692 |
| system.cpu.dcache.WriteReq_hits::total 692 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 8 |
| system.cpu.dcache.LoadLockedReq_hits::total 8 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 8 |
| system.cpu.dcache.StoreCondReq_hits::total 8 |
| system.cpu.dcache.demand_hits::cpu.data 1976 |
| system.cpu.dcache.demand_hits::total 1976 |
| system.cpu.dcache.overall_hits::cpu.data 1976 |
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| system.cpu.dcache.ReadReq_misses::cpu.data 132 |
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| system.cpu.dcache.WriteReq_misses::cpu.data 380 |
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| system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 |
| system.cpu.dcache.LoadLockedReq_misses::total 3 |
| system.cpu.dcache.demand_misses::cpu.data 512 |
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| system.cpu.dcache.overall_misses::cpu.data 512 |
| system.cpu.dcache.overall_misses::total 512 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 9750500 |
| system.cpu.dcache.ReadReq_miss_latency::total 9750500 |
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| system.cpu.dcache.WriteReq_miss_latency::total 27630483 |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 287500 |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 287500 |
| system.cpu.dcache.demand_miss_latency::cpu.data 37380983 |
| system.cpu.dcache.demand_miss_latency::total 37380983 |
| system.cpu.dcache.overall_miss_latency::cpu.data 37380983 |
| system.cpu.dcache.overall_miss_latency::total 37380983 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 1416 |
| system.cpu.dcache.ReadReq_accesses::total 1416 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 1072 |
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| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 |
| system.cpu.dcache.LoadLockedReq_accesses::total 11 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 8 |
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| system.cpu.dcache.demand_accesses::cpu.data 2488 |
| system.cpu.dcache.demand_accesses::total 2488 |
| system.cpu.dcache.overall_accesses::cpu.data 2488 |
| system.cpu.dcache.overall_accesses::total 2488 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.093220 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.093220 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.354478 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.354478 |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.272727 |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.272727 |
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| system.cpu.dcache.overall_miss_rate::total 0.205788 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73867.424242 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 73867.424242 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72711.797368 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 72711.797368 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 95833.333333 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 95833.333333 |
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| system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.732422 |
| system.cpu.dcache.overall_avg_miss_latency::total 73009.732422 |
| system.cpu.dcache.blocked_cycles::no_mshrs 1703 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 27 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.074074 |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
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| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 |
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| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13528999 |
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| system.cpu.icache.tags.total_refs 999 |
| system.cpu.icache.tags.sampled_refs 309 |
| system.cpu.icache.tags.avg_refs 3.233010 |
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| system.cpu.icache.tags.occ_percent::total 0.076310 |
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| system.cpu.icache.demand_accesses::total 1371 |
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| system.cpu.icache.overall_avg_miss_latency::cpu.inst 83764.779570 |
| system.cpu.icache.overall_avg_miss_latency::total 83764.779570 |
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| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 |
| system.cpu.icache.ReadReq_mshr_hits::total 63 |
| system.cpu.icache.demand_mshr_hits::cpu.inst 63 |
| system.cpu.icache.demand_mshr_hits::total 63 |
| system.cpu.icache.overall_mshr_hits::cpu.inst 63 |
| system.cpu.icache.overall_mshr_hits::total 63 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 309 |
| system.cpu.icache.ReadReq_mshr_misses::total 309 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 309 |
| system.cpu.icache.demand_mshr_misses::total 309 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 309 |
| system.cpu.icache.overall_mshr_misses::total 309 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26851498 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 26851498 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26851498 |
| system.cpu.icache.demand_mshr_miss_latency::total 26851498 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26851498 |
| system.cpu.icache.overall_mshr_miss_latency::total 26851498 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.225383 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.225383 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.225383 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.225383 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.225383 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.225383 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86898.051780 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86898.051780 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86898.051780 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 86898.051780 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86898.051780 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 86898.051780 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 246.302600 |
| system.cpu.l2cache.tags.total_refs 0 |
| system.cpu.l2cache.tags.sampled_refs 455 |
| system.cpu.l2cache.tags.avg_refs 0 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 156.427715 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 89.874885 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004774 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.002743 |
| system.cpu.l2cache.tags.occ_percent::total 0.007517 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 455 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 174 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 281 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013885 |
| system.cpu.l2cache.tags.tag_accesses 4095 |
| system.cpu.l2cache.tags.data_accesses 4095 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 80 |
| system.cpu.l2cache.ReadExReq_misses::total 80 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 309 |
| system.cpu.l2cache.ReadCleanReq_misses::total 309 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 66 |
| system.cpu.l2cache.ReadSharedReq_misses::total 66 |
| system.cpu.l2cache.demand_misses::cpu.inst 309 |
| system.cpu.l2cache.demand_misses::cpu.data 146 |
| system.cpu.l2cache.demand_misses::total 455 |
| system.cpu.l2cache.overall_misses::cpu.inst 309 |
| system.cpu.l2cache.overall_misses::cpu.data 146 |
| system.cpu.l2cache.overall_misses::total 455 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7279000 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 7279000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26386000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 26386000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6134500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 6134500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 26386000 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 13413500 |
| system.cpu.l2cache.demand_miss_latency::total 39799500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 26386000 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 13413500 |
| system.cpu.l2cache.overall_miss_latency::total 39799500 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 80 |
| system.cpu.l2cache.ReadExReq_accesses::total 80 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 309 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 309 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 66 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 66 |
| system.cpu.l2cache.demand_accesses::cpu.inst 309 |
| system.cpu.l2cache.demand_accesses::cpu.data 146 |
| system.cpu.l2cache.demand_accesses::total 455 |
| system.cpu.l2cache.overall_accesses::cpu.inst 309 |
| system.cpu.l2cache.overall_accesses::cpu.data 146 |
| system.cpu.l2cache.overall_accesses::total 455 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_miss_rate::total 1 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_miss_rate::total 1 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90987.500000 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90987.500000 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85391.585761 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85391.585761 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92946.969697 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92946.969697 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85391.585761 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91873.287671 |
| system.cpu.l2cache.demand_avg_miss_latency::total 87471.428571 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85391.585761 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91873.287671 |
| system.cpu.l2cache.overall_avg_miss_latency::total 87471.428571 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 80 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 80 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 309 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 309 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 66 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 66 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 309 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 146 |
| system.cpu.l2cache.demand_mshr_misses::total 455 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 309 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 146 |
| system.cpu.l2cache.overall_mshr_misses::total 455 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6479000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6479000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23296000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23296000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5474500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5474500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23296000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11953500 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 35249500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23296000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11953500 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 35249500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80987.500000 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80987.500000 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75391.585761 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75391.585761 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82946.969697 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82946.969697 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75391.585761 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81873.287671 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77471.428571 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75391.585761 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81873.287671 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77471.428571 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 455 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.cpu.toL2Bus.trans_dist::ReadResp 375 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 80 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 80 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 309 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 66 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 618 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 |
| system.cpu.toL2Bus.pkt_count::total 910 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19776 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 |
| system.cpu.toL2Bus.pkt_size::total 29120 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 455 |
| system.cpu.toL2Bus.snoop_fanout::mean 0 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 455 100.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 0 |
| system.cpu.toL2Bus.snoop_fanout::total 455 |
| system.cpu.toL2Bus.reqLayer0.occupancy 227500 |
| system.cpu.toL2Bus.reqLayer0.utilization 1.0 |
| system.cpu.toL2Bus.respLayer0.occupancy 463500 |
| system.cpu.toL2Bus.respLayer0.utilization 2.1 |
| system.cpu.toL2Bus.respLayer1.occupancy 219000 |
| system.cpu.toL2Bus.respLayer1.utilization 1.0 |
| system.membus.snoop_filter.tot_requests 455 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 22347000 |
| system.membus.trans_dist::ReadResp 375 |
| system.membus.trans_dist::ReadExReq 80 |
| system.membus.trans_dist::ReadExResp 80 |
| system.membus.trans_dist::ReadSharedReq 375 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 |
| system.membus.pkt_count::total 910 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 |
| system.membus.pkt_size::total 29120 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 455 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 455 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 455 |
| system.membus.reqLayer0.occupancy 545000 |
| system.membus.reqLayer0.utilization 2.4 |
| system.membus.respLayer1.occupancy 2408250 |
| system.membus.respLayer1.utilization 10.8 |
| |
| ---------- End Simulation Statistics ---------- |
