| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000032 |
| sim_ticks 31821500 |
| final_tick 31821500 |
| sim_freq 1000000000000 |
| host_inst_rate 11620 |
| host_op_rate 11638 |
| host_tick_rate 66593131 |
| host_mem_usage 258956 |
| host_seconds 0.48 |
| sim_insts 5552 |
| sim_ops 5561 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.physmem.bytes_read::cpu.inst 14592 |
| system.physmem.bytes_read::cpu.data 9216 |
| system.physmem.bytes_read::total 23808 |
| system.physmem.bytes_inst_read::cpu.inst 14592 |
| system.physmem.bytes_inst_read::total 14592 |
| system.physmem.num_reads::cpu.inst 228 |
| system.physmem.num_reads::cpu.data 144 |
| system.physmem.num_reads::total 372 |
| system.physmem.bw_read::cpu.inst 458557893 |
| system.physmem.bw_read::cpu.data 289615512 |
| system.physmem.bw_read::total 748173405 |
| system.physmem.bw_inst_read::cpu.inst 458557893 |
| system.physmem.bw_inst_read::total 458557893 |
| system.physmem.bw_total::cpu.inst 458557893 |
| system.physmem.bw_total::cpu.data 289615512 |
| system.physmem.bw_total::total 748173405 |
| system.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 9 |
| system.cpu.pwrStateResidencyTicks::ON 31821500 |
| system.cpu.numCycles 63643 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 5552 |
| system.cpu.committedOps 5561 |
| system.cpu.num_int_alu_accesses 5498 |
| system.cpu.num_fp_alu_accesses 12 |
| system.cpu.num_vec_alu_accesses 0 |
| system.cpu.num_func_calls 282 |
| system.cpu.num_conditional_control_insts 914 |
| system.cpu.num_int_insts 5498 |
| system.cpu.num_fp_insts 12 |
| system.cpu.num_vec_insts 0 |
| system.cpu.num_int_register_reads 7038 |
| system.cpu.num_int_register_writes 3414 |
| system.cpu.num_fp_register_reads 12 |
| system.cpu.num_fp_register_writes 0 |
| system.cpu.num_vec_register_reads 0 |
| system.cpu.num_vec_register_writes 0 |
| system.cpu.num_mem_refs 2162 |
| system.cpu.num_load_insts 1082 |
| system.cpu.num_store_insts 1080 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 63643 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 1196 |
| system.cpu.op_class::No_OpClass 10 0.18% 0.18% |
| system.cpu.op_class::IntAlu 3392 60.90% 61.08% |
| system.cpu.op_class::IntMult 2 0.04% 61.11% |
| system.cpu.op_class::IntDiv 4 0.07% 61.18% |
| system.cpu.op_class::FloatAdd 0 0.00% 61.18% |
| system.cpu.op_class::FloatCmp 0 0.00% 61.18% |
| system.cpu.op_class::FloatCvt 0 0.00% 61.18% |
| system.cpu.op_class::FloatMult 0 0.00% 61.18% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 61.18% |
| system.cpu.op_class::FloatDiv 0 0.00% 61.18% |
| system.cpu.op_class::FloatMisc 0 0.00% 61.18% |
| system.cpu.op_class::FloatSqrt 0 0.00% 61.18% |
| system.cpu.op_class::SimdAdd 0 0.00% 61.18% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 61.18% |
| system.cpu.op_class::SimdAlu 0 0.00% 61.18% |
| system.cpu.op_class::SimdCmp 0 0.00% 61.18% |
| system.cpu.op_class::SimdCvt 0 0.00% 61.18% |
| system.cpu.op_class::SimdMisc 0 0.00% 61.18% |
| system.cpu.op_class::SimdMult 0 0.00% 61.18% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 61.18% |
| system.cpu.op_class::SimdShift 0 0.00% 61.18% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18% |
| system.cpu.op_class::SimdSqrt 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18% |
| system.cpu.op_class::MemRead 1082 19.43% 80.61% |
| system.cpu.op_class::MemWrite 1068 19.17% 99.78% |
| system.cpu.op_class::FloatMemRead 0 0.00% 99.78% |
| system.cpu.op_class::FloatMemWrite 12 0.22% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 5570 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.dcache.tags.replacements 0 |
| system.cpu.dcache.tags.tagsinuse 86.061155 |
| system.cpu.dcache.tags.total_refs 2018 |
| system.cpu.dcache.tags.sampled_refs 144 |
| system.cpu.dcache.tags.avg_refs 14.013889 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 86.061155 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.021011 |
| system.cpu.dcache.tags.occ_percent::total 0.021011 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 144 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 114 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.035156 |
| system.cpu.dcache.tags.tag_accesses 4468 |
| system.cpu.dcache.tags.data_accesses 4468 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 1013 |
| system.cpu.dcache.ReadReq_hits::total 1013 |
| system.cpu.dcache.WriteReq_hits::cpu.data 990 |
| system.cpu.dcache.WriteReq_hits::total 990 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 |
| system.cpu.dcache.LoadLockedReq_hits::total 7 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 8 |
| system.cpu.dcache.StoreCondReq_hits::total 8 |
| system.cpu.dcache.demand_hits::cpu.data 2003 |
| system.cpu.dcache.demand_hits::total 2003 |
| system.cpu.dcache.overall_hits::cpu.data 2003 |
| system.cpu.dcache.overall_hits::total 2003 |
| system.cpu.dcache.ReadReq_misses::cpu.data 61 |
| system.cpu.dcache.ReadReq_misses::total 61 |
| system.cpu.dcache.WriteReq_misses::cpu.data 82 |
| system.cpu.dcache.WriteReq_misses::total 82 |
| system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 |
| system.cpu.dcache.LoadLockedReq_misses::total 1 |
| system.cpu.dcache.demand_misses::cpu.data 143 |
| system.cpu.dcache.demand_misses::total 143 |
| system.cpu.dcache.overall_misses::cpu.data 143 |
| system.cpu.dcache.overall_misses::total 143 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 |
| system.cpu.dcache.ReadReq_miss_latency::total 3843000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 5166000 |
| system.cpu.dcache.WriteReq_miss_latency::total 5166000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 63000 |
| system.cpu.dcache.demand_miss_latency::cpu.data 9009000 |
| system.cpu.dcache.demand_miss_latency::total 9009000 |
| system.cpu.dcache.overall_miss_latency::cpu.data 9009000 |
| system.cpu.dcache.overall_miss_latency::total 9009000 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 1074 |
| system.cpu.dcache.ReadReq_accesses::total 1074 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 1072 |
| system.cpu.dcache.WriteReq_accesses::total 1072 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 |
| system.cpu.dcache.LoadLockedReq_accesses::total 8 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 8 |
| system.cpu.dcache.StoreCondReq_accesses::total 8 |
| system.cpu.dcache.demand_accesses::cpu.data 2146 |
| system.cpu.dcache.demand_accesses::total 2146 |
| system.cpu.dcache.overall_accesses::cpu.data 2146 |
| system.cpu.dcache.overall_accesses::total 2146 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.056797 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.056797 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.076493 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.076493 |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000 |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.066636 |
| system.cpu.dcache.demand_miss_rate::total 0.066636 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.066636 |
| system.cpu.dcache.overall_miss_rate::total 0.066636 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.demand_avg_miss_latency::total 63000 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.overall_avg_miss_latency::total 63000 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 |
| system.cpu.dcache.ReadReq_mshr_misses::total 61 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 |
| system.cpu.dcache.WriteReq_mshr_misses::total 82 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 143 |
| system.cpu.dcache.demand_mshr_misses::total 143 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 143 |
| system.cpu.dcache.overall_mshr_misses::total 143 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8866000 |
| system.cpu.dcache.demand_mshr_miss_latency::total 8866000 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8866000 |
| system.cpu.dcache.overall_mshr_miss_latency::total 8866000 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056797 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056797 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.076493 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.076493 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.125000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066636 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.066636 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066636 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.066636 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.icache.tags.replacements 0 |
| system.cpu.icache.tags.tagsinuse 108.376290 |
| system.cpu.icache.tags.total_refs 6368 |
| system.cpu.icache.tags.sampled_refs 228 |
| system.cpu.icache.tags.avg_refs 27.929825 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 108.376290 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.052918 |
| system.cpu.icache.tags.occ_percent::total 0.052918 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 228 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 82 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 146 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 |
| system.cpu.icache.tags.tag_accesses 13420 |
| system.cpu.icache.tags.data_accesses 13420 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 6368 |
| system.cpu.icache.ReadReq_hits::total 6368 |
| system.cpu.icache.demand_hits::cpu.inst 6368 |
| system.cpu.icache.demand_hits::total 6368 |
| system.cpu.icache.overall_hits::cpu.inst 6368 |
| system.cpu.icache.overall_hits::total 6368 |
| system.cpu.icache.ReadReq_misses::cpu.inst 228 |
| system.cpu.icache.ReadReq_misses::total 228 |
| system.cpu.icache.demand_misses::cpu.inst 228 |
| system.cpu.icache.demand_misses::total 228 |
| system.cpu.icache.overall_misses::cpu.inst 228 |
| system.cpu.icache.overall_misses::total 228 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 14364500 |
| system.cpu.icache.ReadReq_miss_latency::total 14364500 |
| system.cpu.icache.demand_miss_latency::cpu.inst 14364500 |
| system.cpu.icache.demand_miss_latency::total 14364500 |
| system.cpu.icache.overall_miss_latency::cpu.inst 14364500 |
| system.cpu.icache.overall_miss_latency::total 14364500 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 6596 |
| system.cpu.icache.ReadReq_accesses::total 6596 |
| system.cpu.icache.demand_accesses::cpu.inst 6596 |
| system.cpu.icache.demand_accesses::total 6596 |
| system.cpu.icache.overall_accesses::cpu.inst 6596 |
| system.cpu.icache.overall_accesses::total 6596 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.ReadReq_miss_rate::total 0.034566 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.demand_miss_rate::total 0.034566 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.overall_miss_rate::total 0.034566 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.192982 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 63002.192982 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.192982 |
| system.cpu.icache.demand_avg_miss_latency::total 63002.192982 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.192982 |
| system.cpu.icache.overall_avg_miss_latency::total 63002.192982 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 |
| system.cpu.icache.ReadReq_mshr_misses::total 228 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 228 |
| system.cpu.icache.demand_mshr_misses::total 228 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 228 |
| system.cpu.icache.overall_mshr_misses::total 228 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14136500 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 14136500 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14136500 |
| system.cpu.icache.demand_mshr_miss_latency::total 14136500 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14136500 |
| system.cpu.icache.overall_mshr_miss_latency::total 14136500 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.034566 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.034566 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034566 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.034566 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.192982 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.192982 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.192982 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.192982 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.192982 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.192982 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 194.560193 |
| system.cpu.l2cache.tags.total_refs 0 |
| system.cpu.l2cache.tags.sampled_refs 372 |
| system.cpu.l2cache.tags.avg_refs 0 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 108.451522 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 86.108670 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003310 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.002628 |
| system.cpu.l2cache.tags.occ_percent::total 0.005938 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 372 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011353 |
| system.cpu.l2cache.tags.tag_accesses 3348 |
| system.cpu.l2cache.tags.data_accesses 3348 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 82 |
| system.cpu.l2cache.ReadExReq_misses::total 82 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 228 |
| system.cpu.l2cache.ReadCleanReq_misses::total 228 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 62 |
| system.cpu.l2cache.ReadSharedReq_misses::total 62 |
| system.cpu.l2cache.demand_misses::cpu.inst 228 |
| system.cpu.l2cache.demand_misses::cpu.data 144 |
| system.cpu.l2cache.demand_misses::total 372 |
| system.cpu.l2cache.overall_misses::cpu.inst 228 |
| system.cpu.l2cache.overall_misses::cpu.data 144 |
| system.cpu.l2cache.overall_misses::total 372 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4961000 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 4961000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13794500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 13794500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3751000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 3751000 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 13794500 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 8712000 |
| system.cpu.l2cache.demand_miss_latency::total 22506500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 13794500 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 8712000 |
| system.cpu.l2cache.overall_miss_latency::total 22506500 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 82 |
| system.cpu.l2cache.ReadExReq_accesses::total 82 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 228 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 62 |
| system.cpu.l2cache.demand_accesses::cpu.inst 228 |
| system.cpu.l2cache.demand_accesses::cpu.data 144 |
| system.cpu.l2cache.demand_accesses::total 372 |
| system.cpu.l2cache.overall_accesses::cpu.inst 228 |
| system.cpu.l2cache.overall_accesses::cpu.data 144 |
| system.cpu.l2cache.overall_accesses::total 372 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_miss_rate::total 1 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_miss_rate::total 1 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.192982 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.192982 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.192982 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60501.344086 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.192982 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60501.344086 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 82 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 82 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 228 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 228 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 144 |
| system.cpu.l2cache.demand_mshr_misses::total 372 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 144 |
| system.cpu.l2cache.overall_mshr_misses::total 372 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4141000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4141000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11514500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11514500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3131000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3131000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11514500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7272000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 18786500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11514500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7272000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 18786500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.192982 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.192982 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.192982 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.344086 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.192982 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.344086 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 372 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 290 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 82 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 82 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 |
| system.cpu.toL2Bus.pkt_count::total 744 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 |
| system.cpu.toL2Bus.pkt_size::total 23808 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 372 |
| system.cpu.toL2Bus.snoop_fanout::mean 0 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 372 100.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 0 |
| system.cpu.toL2Bus.snoop_fanout::total 372 |
| system.cpu.toL2Bus.reqLayer0.occupancy 186000 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.6 |
| system.cpu.toL2Bus.respLayer0.occupancy 342000 |
| system.cpu.toL2Bus.respLayer0.utilization 1.1 |
| system.cpu.toL2Bus.respLayer1.occupancy 216000 |
| system.cpu.toL2Bus.respLayer1.utilization 0.7 |
| system.membus.snoop_filter.tot_requests 372 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 31821500 |
| system.membus.trans_dist::ReadResp 290 |
| system.membus.trans_dist::ReadExReq 82 |
| system.membus.trans_dist::ReadExResp 82 |
| system.membus.trans_dist::ReadSharedReq 290 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 744 |
| system.membus.pkt_count::total 744 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23808 |
| system.membus.pkt_size::total 23808 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 372 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 372 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 372 |
| system.membus.reqLayer0.occupancy 372500 |
| system.membus.reqLayer0.utilization 1.2 |
| system.membus.respLayer1.occupancy 1860000 |
| system.membus.respLayer1.utilization 5.8 |
| |
| ---------- End Simulation Statistics ---------- |
