dc8018a5c3482008232e6faaa2d96cf20aed7485 - public/gem5

commit	dc8018a5c3482008232e6faaa2d96cf20aed7485	[log] [tgz]
author	Steve Reinhardt <steve.reinhardt@amd.com>	Sat Feb 06 17:21:18 2016 -0800
committer	Steve Reinhardt <steve.reinhardt@amd.com>	Sat Feb 06 17:21:18 2016 -0800
tree	a972ac4544e227397595baf6eeb30e1854f480fc
parent	c8c82f09a282832d919f7eb073a47be838e65b29 [diff]

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

configs/common/CacheConfig.py[diff]
configs/common/Simulation.py[diff]
configs/example/ruby_mem_test.py[diff]
src/arch/alpha/isa/decoder.isa[diff]
src/arch/alpha/linux/linux.hh[diff]
src/arch/alpha/process.cc[diff]
src/arch/alpha/tlb.cc[diff]
src/arch/arm/SConscript[diff]
src/arch/arm/interrupts.cc[diff]
src/arch/arm/isa/bitfields.isa[diff]
src/arch/arm/isa/formats/pred.isa[diff]
src/arch/arm/linux/linux.hh[diff]
src/arch/arm/stacktrace.cc[diff]
src/arch/mips/isa/decoder.isa[diff]
src/arch/mips/linux/linux.hh[diff]
src/arch/mips/linux/process.cc[diff]
src/arch/mips/pagetable.hh[diff]
src/arch/power/SConscript[diff]
src/arch/sparc/interrupts.cc[diff]
src/arch/sparc/linux/linux.hh[diff]
src/arch/sparc/pagetable.hh[diff]
src/arch/x86/cpuid.cc[diff]
src/arch/x86/faults.cc[diff]
src/arch/x86/insts/micromediaop.hh[diff]
src/arch/x86/isa/insts/general_purpose/system_calls.py[diff]
src/arch/x86/isa/insts/romutil.py[diff]
src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py[diff]
src/arch/x86/isa/microops/base.isa[diff]
src/arch/x86/isa/microops/mediaop.isa[diff]
src/arch/x86/isa/microops/regop.isa[diff]
src/arch/x86/process.cc[diff]
src/arch/x86/process.hh[diff]
src/base/cp_annotate.cc[diff]
src/base/cp_annotate.hh[diff]
src/base/cprintf.hh[diff]
src/base/flags.hh[diff]
src/base/inet.cc[diff]
src/base/inet.hh[diff]
src/base/loader/ecoff_object.cc[diff]
src/base/loader/elf_object.cc[diff]
src/base/statistics.cc[diff]
src/cpu/o3/decode_impl.hh[diff]
src/cpu/simple/timing.cc[diff]
src/cpu/testers/directedtest/DirectedGenerator.cc[diff]
src/cpu/testers/directedtest/DirectedGenerator.hh[diff]
src/cpu/testers/directedtest/InvalidateGenerator.cc[diff]
src/cpu/testers/directedtest/InvalidateGenerator.hh[diff]
src/cpu/testers/directedtest/RubyDirectedTester.cc[diff]
src/cpu/testers/directedtest/SeriesRequestGenerator.cc[diff]
src/cpu/testers/directedtest/SeriesRequestGenerator.hh[diff]
src/cpu/testers/networktest/networktest.cc[diff]
src/cpu/timebuf.hh[diff]
src/dev/mc146818.cc[diff]
src/dev/net/i8254xGBe.cc[diff]
src/dev/net/i8254xGBe.hh[diff]
src/dev/net/i8254xGBe_defs.hh[diff]
src/dev/x86/i8042.cc[diff]
src/dev/x86/i8254.hh[diff]
src/dev/x86/intdev.hh[diff]
src/mem/mport.hh[diff]
src/mem/ruby/network/Topology.cc[diff]
src/mem/ruby/network/Topology.hh[diff]
src/mem/ruby/network/fault_model/FaultModel.cc[diff]
src/mem/ruby/network/fault_model/FaultModel.hh[diff]
src/mem/ruby/network/fault_model/FaultModel.py[diff]
src/mem/ruby/network/fault_model/SConscript[diff]
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py[diff]
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh[diff]
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py[diff]
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh[diff]
src/mem/ruby/network/garnet/flexible-pipeline/Router.hh[diff]
src/mem/ruby/network/simple/SimpleLink.cc[diff]
src/mem/slicc/ast/StallAndWaitStatementAST.py[diff]
src/mem/slicc/ast/TypeFieldEnumAST.py[diff]
src/mem/slicc/ast/TypeFieldStateAST.py[diff]
src/python/m5/util/__init__.py[diff]
src/python/swig/event.i[diff]
src/sim/Root.py[diff]
src/sim/eventq.cc[diff]
src/sim/eventq.hh[diff]
src/sim/insttracer.hh[diff]
src/sim/pseudo_inst.cc[diff]
src/unittest/cprintftest.cc[diff]
system/alpha/console/console.c[diff]
tests/configs/memtest-ruby.py[diff]
util/checkpoint-tester.py[diff]
util/compile[diff]
util/m5/m5.c[diff]
util/qdo[diff]
util/statetrace/SConstruct[diff]

90 files changed

tree: a972ac4544e227397595baf6eeb30e1854f480fc

build_opts/
configs/
ext/
src/
system/
tests/
util/
.hgignore
.hgtags
COPYING
LICENSE
README
SConstruct