dd04e7044503046d19b89361edd9a48e14e66ab8 - public/gem5

commit	dd04e7044503046d19b89361edd9a48e14e66ab8	[log] [tgz]
author	Roger Chang <rogerycchang@google.com>	Mon Nov 28 08:27:48 2022 +0000
committer	Roger Chang <rogerycchang@google.com>	Tue Dec 13 05:21:27 2022 +0000
tree	69f1866b830f7c897eec45065713c9eaf20daeac
parent	fa34ebc8535c682717f6dc55649d41b0f16b9762 [diff]

arch-riscv: Implement rv32 zicsr extension

1. Add misc register mstatush, cycleh, timeh, instreth,
   hpmcounter03...hpmcounter31, pmpcfg1, pmpcfg3
2. Implement handling RV32 only registers
3. Implement methods of set time CSR

Change-Id: I5c55c18a0da91977d6e23da24ea3cbcba9f0509b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65733
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/isa.cc[diff]
src/arch/riscv/isa/decoder.isa[diff]
src/arch/riscv/isa/formats/standard.isa[diff]
src/arch/riscv/regs/misc.hh[diff]
src/dev/riscv/clint.cc[diff]

5 files changed