tree 65491479769f4146dc6a150346e3d92ab89a021b
parent 54909088e78d128c17dc79168e75e896ed32d625
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1572883236 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1574070355 +0000

arch-arm: Fix long descriptors cacheability during table walks

Prior to this patch table walks were always cacheable unless
cacheability was globally disabled by SCTLR.C being 0.  Arm allows to
select the memory attributes of table walks via the TCR registers.

For example the TCR.IRGN0 bits:

Inner cacheability attribute for memory associated with translation
table walks using TTBR0_EL1.

IRGN0   Meaning
0b00    Normal memory, Inner Non-cacheable.
0b01    Normal memory, Inner Write-Back Read-Allocate Write-Allocate
        Cacheable.
0b10    Normal memory, Inner Write-Through Read-Allocate No
        Write-Allocate Cacheable.
0b11    Normal memory, Inner Write-Back Read-Allocate No Write-Allocate
        Cacheable.

Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx
(Outer Shareable domain) since in gem5 we consider everything as
Inner Shareable.

Change-Id: If472c218040029c9d165b056a052f522d48d4a82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723
Tested-by: kokoro <noreply+kokoro@google.com>