tree eb2d52f5711b803e6e613b6408722af87122e277
parent 4cca1d89e8a1af1934237a203072e7c832155a39
author Peter <petery.hin@huawei.com> 1612414939 +0800
committer Peter Yuen <petery.hin@huawei.com> 1614051827 +0000

arch-riscv: PLIC Implementation

This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.

Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40598
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>