| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.060161 # Number of seconds simulated |
| sim_ticks 60161166500 # Number of ticks simulated |
| final_tick 60161166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 318648 # Simulator instruction rate (inst/s) |
| host_op_rate 407504 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 270326146 # Simulator tick rate (ticks/s) |
| host_mem_usage 281460 # Number of bytes of host memory used |
| host_seconds 222.55 # Real time elapsed on the host |
| sim_insts 70915150 # Number of instructions simulated |
| sim_ops 90690106 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu.inst 286272 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 7938560 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 8224832 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 286272 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 286272 # Number of instructions bytes read from this memory |
| system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory |
| system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory |
| system.physmem.num_reads::cpu.inst 4473 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 124040 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 128513 # Number of read requests responded to by this memory |
| system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory |
| system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 4758418 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 131954888 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 136713307 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 4758418 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 4758418 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::writebacks 92074810 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::total 92074810 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::writebacks 92074810 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 4758418 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 131954888 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 228788117 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 128513 # Number of read requests accepted |
| system.physmem.writeReqs 86552 # Number of write requests accepted |
| system.physmem.readBursts 128513 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 5537792 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 8224832 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 8086 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 8337 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 8257 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 8155 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 8300 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 8411 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 8071 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 7917 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 8054 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 7612 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 7771 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 7824 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 7888 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 7869 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 7983 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 7973 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 5399 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 5549 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 5478 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 5349 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 5387 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 5588 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 5325 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 5260 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 5187 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 5136 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 5306 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 5279 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 5541 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 5597 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 5706 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 5441 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| system.physmem.totGap 60161135000 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 128513 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 86552 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 116119 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 12356 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 434 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 440 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 4772 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 5355 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 5355 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 5355 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 5358 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 5355 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 5361 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 5363 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 5371 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 5427 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 5453 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 5436 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 5416 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 32871 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 418.627483 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 258.357746 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 362.584215 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 8602 26.17% 26.17% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 6385 19.42% 45.59% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 3434 10.45% 56.04% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 2432 7.40% 63.44% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 2215 6.74% 70.18% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 1621 4.93% 75.11% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 1317 4.01% 79.12% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 1216 3.70% 82.81% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 5649 17.19% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 32871 # Bytes accessed per row activation |
| system.physmem.rdPerTurnAround::samples 5351 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::mean 24.014390 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::gmean 17.652764 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::stdev 347.251849 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::0-1023 5349 99.96% 99.96% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::total 5351 # Reads before turning the bus around for writes |
| system.physmem.wrPerTurnAround::samples 5351 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::mean 16.170435 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::gmean 16.160762 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::stdev 0.581098 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::16 4912 91.80% 91.80% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::17 3 0.06% 91.85% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::18 408 7.62% 99.48% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::19 22 0.41% 99.89% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::20 5 0.09% 99.98% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::total 5351 # Writes before turning the bus around for reads |
| system.physmem.totQLat 3055484500 # Total ticks spent queuing |
| system.physmem.totMemAccLat 5465009500 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 23776.61 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 42526.61 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 136.71 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 92.05 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 136.71 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 92.07 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 1.79 # Data bus utilization in percentage |
| system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing |
| system.physmem.readRowHits 112270 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 69886 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 87.36 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate 80.74 # Row buffer hit rate for writes |
| system.physmem.avgGap 279734.66 # Average gap between requests |
| system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 123657660 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 65710425 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 226208700 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 2513877600.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 2171898930 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 163742880 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 5875439160 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 3027961440 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 8657105625 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 23294071200 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 387.194467 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 54970200750 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 277627750 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 1068464000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 34200521750 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 7885291750 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 3844571250 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 12884690000 # Time in different power states |
| system.physmem_1.actEnergy 111105540 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 59035020 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 449634360 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 225467460 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 2466550320.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 2149128000 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 155904480 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 5311061070 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 3203698560 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 8880552330 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 23012901840 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 382.520865 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 55040293250 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 259491500 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 1048576000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 35050414500 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 8342978750 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 3812745000 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 11646960750 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.branchPred.lookups 14829931 # Number of BP lookups |
| system.cpu.branchPred.condPredicted 9922625 # Number of conditional branches predicted |
| system.cpu.branchPred.condIncorrect 344341 # Number of conditional branches incorrect |
| system.cpu.branchPred.BTBLookups 9711925 # Number of BTB lookups |
| system.cpu.branchPred.BTBHits 6581090 # Number of BTB hits |
| system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.branchPred.BTBHitPct 67.762982 # BTB Hit Percentage |
| system.cpu.branchPred.usedRAS 1720914 # Number of times the RAS was used to get a target. |
| system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. |
| system.cpu.branchPred.indirectLookups 175731 # Number of indirect predictor lookups. |
| system.cpu.branchPred.indirectHits 158482 # Number of indirect target hits. |
| system.cpu.branchPred.indirectMisses 17249 # Number of indirect misses. |
| system.cpu.branchPredindirectMispredicted 24894 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.dtb.walker.walks 0 # Table walker walks requested |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.itb.walker.walks 0 # Table walker walks requested |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.numSyscalls 1946 # Number of system calls |
| system.cpu.pwrStateResidencyTicks::ON 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.numCycles 120322333 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 70915150 # Number of instructions committed |
| system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed |
| system.cpu.discardedOps 1183243 # Number of ops (including micro ops) which were discarded before commit |
| system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| system.cpu.cpi 1.696708 # CPI: cycles per instruction |
| system.cpu.ipc 0.589376 # IPC: instructions per cycle |
| system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction |
| system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction |
| system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction |
| system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::total 90690106 # Class of committed instruction |
| system.cpu.tickCycles 98402849 # Number of cycles that the object actually ticked |
| system.cpu.idleCycles 21919484 # Total number of cycles that the object has spent stopped |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.tags.replacements 156448 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 4067.144261 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 42640706 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 265.601368 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 880402500 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 4067.144261 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 86041472 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 86041472 # Number of data accesses |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.ReadReq_hits::cpu.data 22883524 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 22883524 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 19642139 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 19642139 # number of WriteReq hits |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 83205 # number of SoftPFReq hits |
| system.cpu.dcache.SoftPFReq_hits::total 83205 # number of SoftPFReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 42525663 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 42525663 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 42608868 # number of overall hits |
| system.cpu.dcache.overall_hits::total 42608868 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 47232 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 47232 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 207762 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 207762 # number of WriteReq misses |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 44764 # number of SoftPFReq misses |
| system.cpu.dcache.SoftPFReq_misses::total 44764 # number of SoftPFReq misses |
| system.cpu.dcache.demand_misses::cpu.data 254994 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 254994 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 299758 # number of overall misses |
| system.cpu.dcache.overall_misses::total 299758 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 1840606500 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 1840606500 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 18547852000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 18547852000 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 20388458500 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 20388458500 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 20388458500 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 20388458500 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 22930756 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 22930756 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 127969 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::total 127969 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 42780657 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 42780657 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 42908626 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 42908626 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002060 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.002060 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349803 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.349803 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.005960 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.005960 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.006986 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.006986 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38969.480437 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 38969.480437 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89274.516033 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 89274.516033 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 79956.620548 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 79956.620548 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 68016.394892 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 68016.394892 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.writebacks::writebacks 128143 # number of writebacks |
| system.cpu.dcache.writebacks::total 128143 # number of writebacks |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17700 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 17700 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100723 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 100723 # number of WriteReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 118423 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 118423 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 118423 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 118423 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29532 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 29532 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107039 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 107039 # number of WriteReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23973 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 23973 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 136571 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 136571 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 777371000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 777371000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9483957500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 9483957500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1891396500 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1891396500 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10261328500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 10261328500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12152725000 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 12152725000 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187334 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187334 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26323.005553 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26323.005553 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88602.822336 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88602.822336 # average WriteReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78896.946565 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78896.946565 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75135.486304 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 75135.486304 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75697.160903 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 75697.160903 # average overall mshr miss latency |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.tags.replacements 43580 # number of replacements |
| system.cpu.icache.tags.tagsinuse 1852.022642 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 25068801 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 45622 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 549.489303 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1852.022642 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.904308 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.904308 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 897 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 1022 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 50274470 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 50274470 # Number of data accesses |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.ReadReq_hits::cpu.inst 25068801 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 25068801 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 25068801 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 25068801 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 25068801 # number of overall hits |
| system.cpu.icache.overall_hits::total 25068801 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 45623 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 45623 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 45623 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 45623 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 45623 # number of overall misses |
| system.cpu.icache.overall_misses::total 45623 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 1044947000 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 1044947000 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 1044947000 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 1044947000 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 1044947000 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 1044947000 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 25114424 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 25114424 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 25114424 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 25114424 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 25114424 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 25114424 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22903.951954 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 22903.951954 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 22903.951954 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 22903.951954 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 22903.951954 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 22903.951954 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.writebacks::writebacks 43580 # number of writebacks |
| system.cpu.icache.writebacks::total 43580 # number of writebacks |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45623 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 45623 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 45623 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 45623 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 45623 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 45623 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 999325000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 999325000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 999325000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 999325000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 999325000 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 999325000 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21903.973873 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21903.973873 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.tags.replacements 97173 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 31293.322597 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 268235 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 129941 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 2.064283 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 10984579000 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::writebacks 476.897365 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.117238 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 29439.307994 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::writebacks 0.014554 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042026 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.898416 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.954996 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12846 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17826 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 783 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 3316701 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 3316701 # Number of data accesses |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 128143 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackDirty_hits::total 128143 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackClean_hits::writebacks 39976 # number of WritebackClean hits |
| system.cpu.l2cache.WritebackClean_hits::total 39976 # number of WritebackClean hits |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 4721 # number of ReadExReq hits |
| system.cpu.l2cache.ReadExReq_hits::total 4721 # number of ReadExReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41137 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 41137 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31723 # number of ReadSharedReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::total 31723 # number of ReadSharedReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 41137 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 36444 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 77581 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 41137 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 36444 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 77581 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 102318 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 102318 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4486 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 4486 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21782 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 21782 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 4486 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 124100 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 128586 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 4486 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 124100 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 128586 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9273780500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 9273780500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 495081500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 495081500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2251192500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 2251192500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 495081500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 11524973000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 12020054500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 495081500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 11524973000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 12020054500 # number of overall miss cycles |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 128143 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackDirty_accesses::total 128143 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 39976 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::total 39976 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 107039 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 107039 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45623 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 45623 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53505 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 53505 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 45623 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 206167 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 45623 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 206167 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955895 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.955895 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098328 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098328 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407102 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407102 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098328 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.772997 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.623698 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098328 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.772997 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.623698 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90636.842980 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90636.842980 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110361.457869 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110361.457869 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103351.046736 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103351.046736 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 93478.718523 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 93478.718523 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks |
| system.cpu.l2cache.writebacks::total 86552 # number of writebacks |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits |
| system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses |
| system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4474 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4474 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21722 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21722 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 4474 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 124040 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 128514 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 4474 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 124040 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 128514 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8250600500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8250600500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 448924000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 448924000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029137000 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029137000 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448924000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10279737500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 10728661500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448924000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10279737500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 10728661500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses |
| system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955895 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955895 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098065 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405981 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405981 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.623349 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.623349 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80636.842980 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80636.842980 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100340.634779 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100340.634779 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93413.912163 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93413.912163 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 406195 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 200065 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7850 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.cpu.toL2Bus.trans_dist::ReadResp 99127 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 214695 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackClean 43580 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::CleanEvict 38926 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 45623 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 53505 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134825 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 612361 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5708928 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18475968 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 24184896 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 97173 # Total snoops (count) |
| system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) |
| system.cpu.toL2Bus.snoop_fanout::samples 303340 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0.037578 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.190694 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 291971 96.25% 96.25% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 11339 3.74% 99.99% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 303340 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 374820500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 68448469 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 240848435 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
| system.membus.snoop_filter.tot_requests 222299 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 93862 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadResp 26195 # Transaction distribution |
| system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution |
| system.membus.trans_dist::CleanEvict 7234 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 102318 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 102318 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 26195 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350812 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 350812 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764160 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 13764160 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 128513 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 128513 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 128513 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 588234000 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 677366750 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 1.1 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
