diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index f17ef95..e278c0e 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -492,9 +492,8 @@
                     addr, cmd.dw0.vmid);
             }
             tlb.invalidateVAA(addr, cmd.dw0.vmid);
-
-            if (!cmd.dw1.leaf)
-                walkCache.invalidateVAA(addr, cmd.dw0.vmid);
+            const bool leaf_only = cmd.dw1.leaf ? true : false;
+            walkCache.invalidateVAA(addr, cmd.dw0.vmid, leaf_only);
             break;
         }
 
@@ -509,9 +508,9 @@
                     addr, cmd.dw0.asid, cmd.dw0.vmid);
             }
             tlb.invalidateVA(addr, cmd.dw0.asid, cmd.dw0.vmid);
-
-            if (!cmd.dw1.leaf)
-                walkCache.invalidateVA(addr, cmd.dw0.asid, cmd.dw0.vmid);
+            const bool leaf_only = cmd.dw1.leaf ? true : false;
+            walkCache.invalidateVA(addr, cmd.dw0.asid, cmd.dw0.vmid,
+                                   leaf_only);
             break;
         }
 
diff --git a/src/dev/arm/smmu_v3_caches.cc b/src/dev/arm/smmu_v3_caches.cc
index 63f0b05..d92c544 100644
--- a/src/dev/arm/smmu_v3_caches.cc
+++ b/src/dev/arm/smmu_v3_caches.cc
@@ -1083,15 +1083,40 @@
 }
 
 void
-WalkCache::invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
+WalkCache::invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
+                        const bool leaf_only)
 {
-    panic("%s unimplemented\n", __func__);
+    for (size_t s = 0; s < sets.size(); s++) {
+        Set &set = sets[s];
+
+        for (size_t i = 0; i < set.size(); i++) {
+            Entry &e = set[i];
+
+            if ((!leaf_only || e.leaf) && (e.va & e.vaMask) == (va & e.vaMask)
+                && e.asid == asid && e.vmid == vmid)
+            {
+                e.valid = false;
+            }
+        }
+    }
 }
 
 void
-WalkCache::invalidateVAA(Addr va, uint16_t vmid)
+WalkCache::invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only)
 {
-    panic("%s unimplemented\n", __func__);
+    for (size_t s = 0; s < sets.size(); s++) {
+        Set &set = sets[s];
+
+        for (size_t i = 0; i < set.size(); i++) {
+            Entry &e = set[i];
+
+            if ((!leaf_only || e.leaf) && (e.va & e.vaMask) == (va & e.vaMask)
+                && e.vmid == vmid)
+            {
+                e.valid = false;
+            }
+        }
+    }
 }
 
 void
diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index 50b293c..22ee394 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -310,8 +310,9 @@
                         unsigned stage, unsigned level, bool updStats=true);
     void store(const Entry &incoming);
 
-    void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
-    void invalidateVAA(Addr va, uint16_t vmid);
+    void invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
+                      const bool leaf_only);
+    void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only);
     void invalidateASID(uint16_t asid, uint16_t vmid);
     void invalidateVMID(uint16_t vmid);
     void invalidateAll();