diff --git a/build_opts/NOISA b/build_opts/NOISA
new file mode 100644
index 0000000..dd1f82a
--- /dev/null
+++ b/build_opts/NOISA
@@ -0,0 +1,2 @@
+TARGET_ISA = 'no'
+CPU_MODELS = 'no'
diff --git a/src/arch/noisa/SConsopts b/src/arch/noisa/SConsopts
new file mode 100644
index 0000000..fbfcf05
--- /dev/null
+++ b/src/arch/noisa/SConsopts
@@ -0,0 +1,4 @@
+
+Import('*')
+
+all_isa_list.append('no')
diff --git a/src/arch/noisa/cpu_dummy.hh b/src/arch/noisa/cpu_dummy.hh
new file mode 100644
index 0000000..2b83f5e
--- /dev/null
+++ b/src/arch/noisa/cpu_dummy.hh
@@ -0,0 +1,6 @@
+
+class BaseCPU
+{
+  public:
+    static int numSimulatedInstructions() { return 0; }
+};
diff --git a/src/base/SConscript b/src/base/SConscript
index 9ddeb87..91671f8 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -56,7 +56,8 @@
 Source('random.cc')
 Source('random_mt.cc')
 Source('range.cc')
-Source('remote_gdb.cc')
+if env['TARGET_ISA'] != 'no':
+    Source('remote_gdb.cc')
 Source('sat_counter.cc')
 Source('socket.cc')
 Source('statistics.cc')
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 35e92a1..99308c2 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 #################################################################
 #
 # Generate StaticInst execute() method signatures.
diff --git a/src/cpu/nocpu/SConsopts b/src/cpu/nocpu/SConsopts
new file mode 100644
index 0000000..0baef0a
--- /dev/null
+++ b/src/cpu/nocpu/SConsopts
@@ -0,0 +1,4 @@
+
+Import('*')
+
+CpuModel('no', '', '', { '': '' })
diff --git a/src/dev/SConscript b/src/dev/SConscript
index c09ec3d..7cdea79 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -31,6 +31,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if env['FULL_SYSTEM']:
     SimObject('BadDevice.py')
     SimObject('CopyEngine.py')
diff --git a/src/kern/SConscript b/src/kern/SConscript
index fc682ae..145f0d9 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if env['FULL_SYSTEM']:
     Source('kernel_stats.cc')
     Source('system_events.cc')
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 46de3eb..52c5307 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -33,21 +33,23 @@
 SimObject('Bridge.py')
 SimObject('Bus.py')
 SimObject('MemObject.py')
-SimObject('PhysicalMemory.py')
 
 Source('bridge.cc')
 Source('bus.cc')
-Source('dram.cc')
 Source('mem_object.cc')
 Source('packet.cc')
-Source('physical.cc')
 Source('port.cc')
 Source('tport.cc')
 Source('mport.cc')
 
+if env['TARGET_ISA'] != 'no':
+    SimObject('PhysicalMemory.py')
+    Source('dram.cc')
+    Source('physical.cc')
+
 if env['FULL_SYSTEM']:
     Source('vport.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
     Source('translating_port.cc')
 
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 3b8bdb0..781521d 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 SimObject('BaseCache.py')
 
 Source('base.cc')
diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index 7314b5c..9d05a8e 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('ghb.cc')
 Source('stride.cc')
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 37ed5dc..d640a9f 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 1f7509d..339787a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -37,6 +37,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if not env['RUBY']:
     Return()
 
diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh
index b18a2a7..ab22df8 100644
--- a/src/python/swig/pyobject.hh
+++ b/src/python/swig/pyobject.hh
@@ -31,10 +31,8 @@
 #include <Python.h>
 
 #include "base/types.hh"
-#include "cpu/base.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_object.hh"
-#include "sim/system.hh"
 
 extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
 SimObject *resolveSimObject(const std::string &name);
diff --git a/src/sim/SConscript b/src/sim/SConscript
index b1e3a4b..97c6dda 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -32,28 +32,30 @@
 
 SimObject('BaseTLB.py')
 SimObject('Root.py')
-SimObject('System.py')
 SimObject('InstTracer.py')
 
 Source('async.cc')
 Source('core.cc')
 Source('debug.cc')
 Source('eventq.cc')
-Source('faults.cc')
 Source('init.cc')
 Source('main.cc', bin_only=True)
-Source('pseudo_inst.cc')
 Source('root.cc')
 Source('serialize.cc')
 Source('sim_events.cc')
 Source('sim_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
-Source('system.cc')
+
+if env['TARGET_ISA'] != 'no':
+    SimObject('System.py')
+    Source('faults.cc')
+    Source('pseudo_inst.cc')
+    Source('system.cc')
 
 if env['FULL_SYSTEM']:
     Source('arguments.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
     Source('tlb.cc')
     SimObject('Process.py')
 
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 373a3f2..07e1b23 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -39,7 +39,14 @@
 #include "base/hostinfo.hh"
 #include "base/statistics.hh"
 #include "base/time.hh"
+
+#include "config/the_isa.hh"
+#if THE_ISA == NO_ISA
+#include "arch/noisa/cpu_dummy.hh"
+#else
 #include "cpu/base.hh"
+#endif
+
 #include "sim/eventq.hh"
 
 using namespace std;
diff --git a/src/unittest/SConscript b/src/unittest/SConscript
index 1c19591..91ead52 100644
--- a/src/unittest/SConscript
+++ b/src/unittest/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 UnitTest('bitvectest', 'bitvectest.cc')
 UnitTest('circletest', 'circletest.cc')
 UnitTest('cprintftest', 'cprintftest.cc')