diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 8e3a1f8..2e9700f 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -87,7 +87,7 @@
 
             self.symtab.registerSym(param.ident, var)
 
-            if str(param.type_ast.type) == "Prefetcher":
+            if str(param.type_ast.type) == "RubyPrefetcher":
                 self.prefetchers.append(var)
 
         self.states = OrderedDict()