/*
 * Copyright (c) 2012, 2018 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#include "cpu/simple/noncaching.hh"

#include <cassert>

#include "arch/generic/decoder.hh"

namespace gem5
{

NonCachingSimpleCPU::NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)
    : AtomicSimpleCPU(p)
{
    assert(p.numThreads == 1);
    fatal_if(!FullSystem && p.workload.size() != 1,
             "only one workload allowed");
}

void
NonCachingSimpleCPU::verifyMemoryMode() const
{
    if (!(system->isAtomicMode() && system->bypassCaches())) {
        fatal("The direct CPU requires the memory system to be in the "
              "'atomic_noncaching' mode.\n");
    }
}

Tick
NonCachingSimpleCPU::sendPacket(RequestPort &port, const PacketPtr &pkt)
{
    MemBackdoorPtr bd = nullptr;
    Tick latency = port.sendAtomicBackdoor(pkt, bd);

    // If the target gave us a backdoor for next time and we didn't
    // already have it, record it.
    if (bd && memBackdoors.insert(bd->range(), bd) != memBackdoors.end()) {
        // Install a callback to erase this backdoor if it goes away.
        auto callback = [this](const MemBackdoor &backdoor) {
                for (auto it = memBackdoors.begin();
                        it != memBackdoors.end(); it++) {
                    if (it->second == &backdoor) {
                        memBackdoors.erase(it);
                        return;
                    }
                }
                panic("Got invalidation for unknown memory backdoor.");
            };
        bd->addInvalidationCallback(callback);
    }
    return latency;
}

Tick
NonCachingSimpleCPU::fetchInstMem()
{
    auto bd_it = memBackdoors.contains(ifetch_req->getPaddr());
    if (bd_it == memBackdoors.end())
        return AtomicSimpleCPU::fetchInstMem();

    auto &decoder = threadInfo[curThread]->thread->decoder;

    auto *bd = bd_it->second;
    Addr offset = ifetch_req->getPaddr() - bd->range().start();
    memcpy(decoder->moreBytesPtr(), bd->ptr() + offset, ifetch_req->getSize());
    return 0;
}

} // namespace gem5