tree 7ccac38976eeaf5e683d1a4d60046774b65c3ca9
parent 008ae4b0650d9249ec719985eb5aa0726d643ed0
author Isaac Richter <isaac.richter@rochester.edu> 1522418471 -0400
committer Jason Lowe-Power <jason@lowepower.com> 1571155366 +0000

arch-x86: Make LFENCE a serializing instruction

According to the Intel SDM, no instruction following an LFENCE can begin
execution until after the LFENCE has executed. (This is
less strict than an actual serializing instruction, such as CPUID.)

Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure
that no future instruction is fetched until after the serializing
instruction is completed.

By contrast, LFENCE (and other memory-ordering instructions) allows
future instructions to have been fetched; it just prohibits them from
being executed.

Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Signed-off-by: Isaac Richter <isaac.richter@rochester.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>