tests: Re-enable the realview-o3-checker test
We are using the VExpress_GEM5_V1 platform for this test.
This is currently needed as the checker is GICv3 incompatible:
When validating MiscReg cpu interface register (MISCREG_ICC_*) updates
the underlying ISA storage is checked. However the content of some of
those registers is hardcoded in the GICv3 logic
JIRA: https://gem5.atlassian.net/browse/GEM5-364
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8cfbba6d9869232fdb8475d17d15d15b61dfab87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46626
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2 files changed
