tree ef1931b5aaad562807fdd2cec75b80dbcf4331a0
parent 2a818db77ab5fe5cc7d716dd2aa88241550045a7
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1567419975 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1567800034 +0000

dev-arm: State update when setting MISCREG_ICC_IGRPENx register

This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).

Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>