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from m5.params import *
from m5.objects.SubSystem import SubSystem


class CpuCluster(SubSystem):
    type = "CpuCluster"
    cxx_header = "cpu/cluster.hh"
    cxx_class = "gem5::CpuCluster"

    _NUM_CPUS = 0
    _NUM_CLUSTERS = 0

    voltage_domain = Param.VoltageDomain("Voltage domain")
    clk_domain = Param.ClockDomain("Clock domain")

    def __iter__(self):
        return iter(self.cpus)

    def generate_cpus(self, cpu_type: "BaseCPU", num_cpus: int):
        """
        Instantiates the cpus within the cluster provided
        theit type and their number.

        :param cpu_type: The cpu class
        :param num_cpus: The number of cpus within the cluster
        """
        self.cpus = [
            cpu_type(
                cpu_id=CpuCluster._NUM_CPUS + idx, clk_domain=self.clk_domain
            )
            for idx in range(num_cpus)
        ]

        for cpu in self.cpus:
            cpu.createThreads()
            cpu.createInterruptController()
            cpu.socket_id = CpuCluster._NUM_CLUSTERS

        # "Register" the cluster/cpus by augmenting the
        # class variables
        CpuCluster._NUM_CPUS += num_cpus
        CpuCluster._NUM_CLUSTERS += 1

    def connect(self, membus: "SystemXBar"):
        """
        Connects every cpu within the cluster with the
        provided bus

        :param membus: The system crossbar
        """
        for cpu in self.cpus:
            cpu.connectBus(membus)

    def memory_mode(self) -> "MemoryMode":
        return type(self.cpus[0]).memory_mode()

    def require_caches(self) -> bool:
        return type(self.cpus[0]).require_caches()