arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 654608a..cdc44cd 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -65,7 +65,8 @@
_vecRegRenameMode(Enums::Full),
pmu(p->pmu),
haveGICv3CPUInterface(false),
- impdefAsNop(p->impdef_nop)
+ impdefAsNop(p->impdef_nop),
+ afterStartup(false)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
@@ -406,6 +407,8 @@
gicv3CpuInterface->setThreadContext(tc);
}
}
+
+ afterStartup = true;
}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1931306..b4689d7 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -105,6 +105,8 @@
*/
bool impdefAsNop;
+ bool afterStartup;
+
/** MiscReg metadata **/
struct MiscRegLUTEntry {
uint32_t lower; // Lower half mapped to this register
@@ -706,6 +708,16 @@
Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
+ /** Getter for haveGICv3CPUInterface */
+ bool haveGICv3CpuIfc() const
+ {
+ // haveGICv3CPUInterface is initialized at startup time, hence
+ // trying to read its value before the startup stage will lead
+ // to an error
+ assert(afterStartup);
+ return haveGICv3CPUInterface;
+ }
+
Enums::VecRegRenameMode
vecRegRenameMode() const
{