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# Copyright (c) 2012-2013, 2021 ARM Limited
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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from m5.params import *
from m5.objects.AbstractMemory import AbstractMemory
from m5.util.fdthelper import FdtNode, FdtPropertyWords
class CfiMemory(AbstractMemory):
type = 'CfiMemory'
cxx_header = "mem/cfi_mem.hh"
cxx_class = 'gem5::memory::CfiMemory'
port = ResponsePort("Response port")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
# The memory bandwidth limit default is set to 12.8GB/s which is
# representative of a x64 DDR3-1600 channel.
bandwidth = Param.MemoryBandwidth('12.8GB/s',
"Combined read and write bandwidth")
vendor_id = Param.UInt16(0, "vendor ID")
device_id = Param.UInt16(0, "device ID")
blk_size = Param.UInt32(64 * 1024, "Block size in bytes")
bank_width = Param.UInt16(4, "width in bytes of flash interface")