arm: Fix how a bitfield is extracted in some SVE instructions.
These instructions were extracting a bitfield by masking it, but then
didn't shift the bit into the correct position. They were then
comparing it with 1, which clang 11 correctly complained would always
be false. That warning became an error which broke the build.
This fixes that problem by switching that line and the few surrounding
lines to use the bits() function which removes the need to manually
mask or shift values. That makes it less likely for there to be a
mistake, and also makes it more obvious which bits are being accessed.
Change-Id: I692214f898e90dc7d5de460d1da2ef6aefda4fb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25224
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index c46a34d..612e3c7 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2986,10 +2986,10 @@
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());'''
code += '''
- uint32_t sel_a = rot & 0x1;
+ uint32_t sel_a = bits(rot, 0);
uint32_t sel_b = sel_a ? 0 : 1;
- bool neg_i = (rot & 0x2) == 1;
- bool neg_r = (rot & 0x1) != (rot & 0x2);'''
+ bool neg_i = bits(rot, 1);
+ bool neg_r = bits(rot, 0) != bits(rot, 1);'''
if predType == PredType.NONE:
code += '''
uint32_t eltspersegment = 16 / (2 * sizeof(Element));'''
