diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 29c4138..d098692 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -224,6 +224,11 @@
             if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
                 mem_ctrl.ranks_per_channel = opt_mem_ranks
 
+            # Enable low-power DRAM states if option is set
+            if issubclass(cls, m5.objects.DRAMCtrl):
+                mem_ctrl.enable_dram_powerdown = \
+                        options.enable_dram_powerdown
+
             if opt_elastic_trace_en:
                 mem_ctrl.latency = '1ns'
                 print("For elastic trace, over-riding Simple Memory "
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 4279b80..f6fa0d0 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -104,6 +104,8 @@
     parser.add_option("--mem-size", action="store", type="string",
                       default="512MB",
                       help="Specify the physical memory size (single memory)")
+    parser.add_option("--enable-dram-powerdown", action="store_true",
+                       help="Enable low-power states in DRAMCtrl")
 
 
     parser.add_option("--memchecker", action="store_true")
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 2d69ac1..c9ae251 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -130,6 +130,11 @@
             else:
                 mem_ctrl.port = dir_cntrl.memory
 
+            # Enable low-power DRAM states if option is set
+            if issubclass(MemConfig.get(options.mem_type), DRAMCtrl):
+                mem_ctrl.enable_dram_powerdown = \
+                        options.enable_dram_powerdown
+
         index += 1
         dir_cntrl.addr_ranges = dir_ranges
 
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 93ea7d5..14db3d3 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -135,6 +135,10 @@
     # to be instantiated for a multi-channel configuration
     channels = Param.Unsigned(1, "Number of channels")
 
+    # Enable DRAM powerdown states if True. This is False by default due to
+    # performance being lower when enabled
+    enable_dram_powerdown = Param.Bool(False, "Enable powerdown states")
+
     # For power modelling we need to know if the DRAM has a DLL or not
     dll = Param.Bool(True, "DRAM has DLL or not")
 
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 08465aa..06c540b 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -97,7 +97,7 @@
     backendLatency(p->static_backend_latency),
     nextBurstAt(0), prevArrival(0),
     nextReqTime(0), activeRank(0), timeStampOffset(0),
-    lastStatsResetTick(0)
+    lastStatsResetTick(0), enableDRAMPowerdown(p->enable_dram_powerdown)
 {
     // sanity check the ranks since we rely on bit slicing for the
     // address decoding
@@ -705,7 +705,7 @@
     // track if this is the last packet before idling
     // and that there are no outstanding commands to this rank
     if (dram_pkt->rankRef.isQueueEmpty() &&
-        dram_pkt->rankRef.outstandingEvents == 0) {
+        dram_pkt->rankRef.outstandingEvents == 0 && enableDRAMPowerdown) {
         // verify that there are no events scheduled
         assert(!dram_pkt->rankRef.activateEvent.scheduled());
         assert(!dram_pkt->rankRef.prechargeEvent.scheduled());
@@ -1856,7 +1856,8 @@
     if (numBanksActive == 0) {
         // no reads to this rank in the Q and no pending
         // RD/WR or refresh commands
-        if (isQueueEmpty() && outstandingEvents == 0) {
+        if (isQueueEmpty() && outstandingEvents == 0 &&
+            memory.enableDRAMPowerdown) {
             // should still be in ACT state since bank still open
             assert(pwrState == PWR_ACT);
 
@@ -2057,7 +2058,7 @@
 
             // Force PRE power-down if there are no outstanding commands
             // in Q after refresh.
-            } else if (isQueueEmpty()) {
+            } else if (isQueueEmpty() && memory.enableDRAMPowerdown) {
                 // still have refresh event outstanding but there should
                 // be no other events outstanding
                 assert(outstandingEvents == 1);
@@ -2328,7 +2329,8 @@
         // will issue refresh immediately upon entry
         if (pwrStatePostRefresh == PWR_PRE_PDN && isQueueEmpty() &&
            (memory.drainState() != DrainState::Draining) &&
-           (memory.drainState() != DrainState::Drained)) {
+           (memory.drainState() != DrainState::Drained) &&
+           memory.enableDRAMPowerdown) {
             DPRINTF(DRAMState, "Rank %d bypassing refresh and transitioning "
                     "to self refresh at %11u tick\n", rank, curTick());
             powerDownSleep(PWR_SREF, curTick());
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 54826e0..7de0872 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -1140,6 +1140,9 @@
     /** The time when stats were last reset used to calculate average power */
     Tick lastStatsResetTick;
 
+    /** Enable or disable DRAM powerdown states. */
+    bool enableDRAMPowerdown;
+
     /**
      * Upstream caches need this packet until true is returned, so
      * hold it for deletion until a subsequent call