diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
deleted file mode 100644
index 961681a..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ /dev/null
@@ -1,1784 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727:0:0:0:0
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
deleted file mode 100755
index a8a3639..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
deleted file mode 100755
index 98915ba..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:46
-gem5 executing on e108600-lin, pid 28076
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1893220881500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
deleted file mode 100644
index 75078a9..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ /dev/null
@@ -1,1243 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.893228                       # Number of seconds simulated
-sim_ticks                                1893227678500                       # Number of ticks simulated
-final_tick                               1893227678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31053                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31053                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1047239405                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384600                       # Number of bytes of host memory used
-host_seconds                                  1807.83                       # Real time elapsed on the host
-sim_insts                                    56138739                       # Number of instructions simulated
-sim_ops                                      56138739                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst           1046400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24860352                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25907712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1046400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1046400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7566528                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7566528                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16350                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404808                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118227                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118227                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               552707                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13131200                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               507                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13684414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          552707                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             552707                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3996629                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3996629                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3996629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              552707                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13131200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17681043                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404808                       # Number of read requests accepted
-system.physmem.writeReqs                       118227                       # Number of write requests accepted
-system.physmem.readBursts                      404808                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118227                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25900800                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6912                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7564480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25907712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7566528                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      108                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25487                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25708                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25811                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25775                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25223                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24955                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24789                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24582                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25110                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25258                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25516                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24876                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24528                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25560                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25799                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25723                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7831                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7673                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8069                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7745                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7318                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6942                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6789                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6426                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7239                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6872                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7384                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6889                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7081                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8010                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7995                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7932                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          72                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1893218795000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404808                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118227                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      189                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63391                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      527.918474                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     322.301426                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     413.348187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14401     22.72%     22.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11109     17.52%     40.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4782      7.54%     47.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3159      4.98%     52.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2221      3.50%     56.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2316      3.65%     59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1932      3.05%     62.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1599      2.52%     65.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21872     34.50%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63391                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5234                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.317348                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2918.457754                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5231     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5234                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5234                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.582155                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.722612                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.927693                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4724     90.26%     90.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              39      0.75%     91.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             163      3.11%     94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               4      0.08%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               3      0.06%     94.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              11      0.21%     94.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               8      0.15%     94.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               2      0.04%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              33      0.63%     95.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               4      0.08%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            144      2.75%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            23      0.44%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             9      0.17%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             3      0.06%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             7      0.13%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             3      0.06%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            10      0.19%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             5      0.10%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            14      0.27%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            10      0.19%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.06%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             5      0.10%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-359             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5234                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5912751750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13500876750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14610.21                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33360.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.68                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.68                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.00                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363798                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95706                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.89                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3619678.98                       # Average gap between requests
-system.physmem.pageHitRate                      87.87                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  222139680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  118070040                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1444636200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                306899460                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           4706913120.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             4768209600                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              303610560                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy       10937646210                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        5541404160                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy       443214367815                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             471564552855                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              249.079684                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1881862215000                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      479498250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1999510000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   1843562153500                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  14430696500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8769616250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  23986204000                       # Time in different power states
-system.physmem_1.actEnergy                  230472060                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122498805                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1444921800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                310078440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           4819392240.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             4890695190                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              314585760                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy       11137759530                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        5641159680                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy       443008801920                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             471922426215                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              249.268712                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1881676600250                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      514596250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2047516000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   1842563195250                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN  14690458500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8987140500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  24424772000                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                15251875                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13114549                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            526465                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12070936                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 4577345                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             37.920382                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  863154                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33512                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6526029                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             541717                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5984312                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       221941                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9319487                       # DTB read hits
-system.cpu.dtb.read_misses                      17755                       # DTB read misses
-system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   764786                       # DTB read accesses
-system.cpu.dtb.write_hits                     6392965                       # DTB write hits
-system.cpu.dtb.write_misses                      2560                       # DTB write misses
-system.cpu.dtb.write_acv                          158                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298884                       # DTB write accesses
-system.cpu.dtb.data_hits                     15712452                       # DTB hits
-system.cpu.dtb.data_misses                      20315                       # DTB misses
-system.cpu.dtb.data_acv                           369                       # DTB access violations
-system.cpu.dtb.data_accesses                  1063670                       # DTB accesses
-system.cpu.itb.fetch_hits                     4023125                       # ITB hits
-system.cpu.itb.fetch_misses                      6293                       # ITB misses
-system.cpu.itb.fetch_acv                          687                       # ITB acv
-system.cpu.itb.fetch_accesses                 4029418                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12752                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6376                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     281784609.786700                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439970621.768515                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6376    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value       121000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6376                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     96569006500                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        193159059                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56138739                       # Number of instructions committed
-system.cpu.committedOps                      56138739                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2973387                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      6376                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3593296298                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.440745                       # CPI: cycles per instruction
-system.cpu.ipc                               0.290635                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass             3199075      5.70%      5.70% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                36194440     64.47%     70.17% # Class of committed instruction
-system.cpu.op_class_0::IntMult                  60814      0.11%     70.28% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                       0      0.00%     70.28% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd                 38079      0.07%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatMult                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                  3636      0.01%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::MemRead                9174678     16.34%     86.70% # Class of committed instruction
-system.cpu.op_class_0::MemWrite               6234348     11.11%     97.80% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead            144497      0.26%     98.06% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite           137980      0.25%     98.31% # Class of committed instruction
-system.cpu.op_class_0::IprAccess               951192      1.69%    100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                 56138739                       # Class of committed instruction
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211522                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74796     40.93%     40.93% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1905      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105900     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182732                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73429     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1905      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73429     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148894                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1837688968000     97.07%     97.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                86405500      0.00%     97.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               711997500      0.04%     97.11% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             54739315500      2.89%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1893226686500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981724                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693381                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814822                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4173      2.17%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175565     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6808      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5130      2.67%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192456                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5875                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1904                      
-system.cpu.kern.mode_good::user                  1736                      
-system.cpu.kern.mode_good::idle                   168                      
-system.cpu.kern.mode_switch_good::kernel     0.324085                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392375                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        37303090500      1.97%      1.97% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4315388500      0.23%      2.20% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1851608197500     97.80%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
-system.cpu.tickCycles                        85358190                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       107800869                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1394352                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.980074                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13943564                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1394864                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.996361                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          99338500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.980074                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999961                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999961                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63916074                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63916074                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7983580                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7983580                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5577346                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5577346                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183586                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183586                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199016                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199016                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13560926                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13560926                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13560926                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13560926                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1096421                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1096421                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       573901                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573901                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        16452                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        16452                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1670322                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1670322                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1670322                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1670322                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33580747500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33580747500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  25364054000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  25364054000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223095000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    223095000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  58944801500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  58944801500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  58944801500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  58944801500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9080001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9080001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6151247                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6151247                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200038                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200038                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15231248                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15231248                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15231248                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15231248                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120751                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120751                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093298                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093298                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082244                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082244                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.109664                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.109664                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.109664                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.109664                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35289.484004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35289.484004                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       837673                       # number of writebacks
-system.cpu.dcache.writebacks::total            837673                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21981                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21981                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269878                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269878                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       291859                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       291859                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       291859                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       291859                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074440                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074440                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304023                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304023                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16449                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16449                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378463                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378463                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378463                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378463                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9623                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9623                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16553                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16553                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32016506000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  32016506000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12938125500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12938125500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205942500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205942500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  44954631500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  44954631500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  44954631500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  44954631500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1534159000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1534159000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1534159000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1534159000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118330                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118330                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049425                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049425                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082229                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082229                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090502                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090502                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090502                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090502                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1477259                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.256262                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            19240724                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1477770                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             13.020107                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       36168160500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.256262                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          398                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          22196619                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         22196619                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     19240727                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        19240727                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      19240727                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         19240727                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     19240727                       # number of overall hits
-system.cpu.icache.overall_hits::total        19240727                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1477946                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1477946                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1477946                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1477946                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1477946                       # number of overall misses
-system.cpu.icache.overall_misses::total       1477946                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20694155000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20694155000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20694155000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20694155000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20694155000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20694155000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20718673                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20718673                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20718673                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20718673                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20718673                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20718673                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071334                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071334                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071334                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071334                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071334                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071334                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14001.969625                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14001.969625                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1477259                       # number of writebacks
-system.cpu.icache.writebacks::total           1477259                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1477946                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1477946                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1477946                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1477946                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1477946                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1477946                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19216209000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  19216209000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19216209000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  19216209000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19216209000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  19216209000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071334                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071334                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071334                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071334                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071334                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071334                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           339629                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65408.640121                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5336861                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           405151                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.172523                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6812650000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   268.308507                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5784.509565                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.004094                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088265                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.905698                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998057                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          585                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5148                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59336                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46345268                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46345268                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       837673                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       837673                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1476684                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1476684                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           16                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           16                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187384                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187384                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1461541                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1461541                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       818635                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       818635                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1461541                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1006019                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2467560                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1461541                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1006019                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2467560                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116650                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116650                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272221                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       272221                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        16351                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388871                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        405222                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        16351                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388871                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405222                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       331500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       331500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10508664000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10508664000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1613902000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1613902000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  21967740000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  21967740000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1613902000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  32476404000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  34090306000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1613902000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  32476404000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  34090306000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       837673                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       837673                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1476684                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1476684                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           22                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           22                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304034                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304034                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1477892                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1477892                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1090856                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1090856                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1477892                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1394890                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2872782                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1477892                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1394890                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2872782                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.272727                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.272727                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383674                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383674                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011064                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011064                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249548                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249548                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011064                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.278783                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.141056                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011064                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.278783                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.141056                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        55250                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        55250                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        76715                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76715                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116650                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116650                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16351                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16351                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272221                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272221                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16351                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388871                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405222                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16351                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388871                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405222                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9623                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9623                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16553                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16553                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       271500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       271500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9342164000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9342164000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1450392000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1450392000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19248668000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19248668000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1450392000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28590832000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  30041224000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1450392000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28590832000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30041224000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447515000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447515000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447515000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447515000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.272727                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383674                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383674                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011064                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011064                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249548                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249548                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011064                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278783                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141056                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011064                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278783                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141056                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        45250                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        45250                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5744469                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2871707                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2386                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          999                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          999                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2575864                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9623                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9623                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       914388                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1477259                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       819593                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           22                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304034                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304034                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1477946                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq          237                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp            2                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4433097                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4217440                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8650537                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    189129664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142936828                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          332066492                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      340239                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4923200                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3229438                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001049                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.032373                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3226050     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3388      0.10%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3229438                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5200254500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       292883                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2217065706                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2104067991                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51175                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51175                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33106                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116556                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20408                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44348                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705956                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5413500                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               792000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              180500                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15611000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2305500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5971500                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216263272                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23483000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.299521                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1735874841000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.299521                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081220                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081220                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     29884383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29884383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4948356889                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4948356889                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4978241272                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4978241272                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4978241272                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4978241272                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 172742.098266                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119310.755470                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119310.755470                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs          1846                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   14                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs   131.857143                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     21234383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     21234383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2868303297                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2868303297                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2889537680                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2889537680                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2889537680                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2889537680                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 69251.951588                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 69251.951588                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        827499                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       381391                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          524                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295651                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9623                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9623                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       118227                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262247                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              138                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116518                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116518                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288745                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           24                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp          124                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33106                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148786                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           48                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1265365                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44348                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30816512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30860860                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33518588                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              558                       # Total snoops (count)
-system.membus.snoopTraffic                      27584                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            463506                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001454                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.038105                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  462832     99.85%     99.85% # Request fanout histogram
-system.membus.snoop_fanout::1                     674      0.15%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              463506                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30386000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1319436087                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               30000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160035750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy            1079521                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
deleted file mode 100644
index b49f55c..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
deleted file mode 100644
index 7fa6515..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ /dev/null
@@ -1,2271 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727:0:0:0:0
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu0.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu0.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu0.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
-eventq_index=0
-
-[system.cpu0.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu0.fuPool.FUList0.opList
-
-[system.cpu0.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
-
-[system.cpu0.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
-
-[system.cpu0.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
-
-[system.cpu0.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu0.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList
-
-[system.cpu0.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
-
-[system.cpu0.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList6.opList
-
-[system.cpu0.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
-
-[system.cpu0.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList8.opList
-
-[system.cpu0.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu0.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu1.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=1
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu1.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu1.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
-eventq_index=0
-
-[system.cpu1.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu1.fuPool.FUList0.opList
-
-[system.cpu1.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
-
-[system.cpu1.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
-
-[system.cpu1.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
-
-[system.cpu1.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu1.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList
-
-[system.cpu1.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
-
-[system.cpu1.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList6.opList
-
-[system.cpu1.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
-
-[system.cpu1.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList8.opList
-
-[system.cpu1.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu1.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu0
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
deleted file mode 100755
index 9acbae0..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
deleted file mode 100755
index 1abbf97..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ /dev/null
@@ -1,16 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:46
-gem5 executing on e108600-lin, pid 28085
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 133768500
-Exiting @ tick 1907549438500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
deleted file mode 100644
index 1e6aa4a..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ /dev/null
@@ -1,2349 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.910457                       # Number of seconds simulated
-sim_ticks                                1910457097500                       # Number of ticks simulated
-final_tick                               1910457097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 237868                       # Simulator instruction rate (inst/s)
-host_op_rate                                   237868                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8017235800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 340828                       # Number of bytes of host memory used
-host_seconds                                   238.29                       # Real time elapsed on the host
-sim_insts                                    56682446                       # Number of instructions simulated
-sim_ops                                      56682446                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           856512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24438912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           120704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           888384                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26305472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       856512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       120704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          977216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7909632                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7909632                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            381858                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1886                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             13881                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                411023                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123588                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123588                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              448328                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12792180                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               63181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              465011                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13769203                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         448328                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          63181                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             511509                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4140178                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4140178                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4140178                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             448328                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12792180                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              63181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             465011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              502                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17909381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        411023                       # Number of read requests accepted
-system.physmem.writeReqs                       123588                       # Number of write requests accepted
-system.physmem.readBursts                      411023                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123588                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26298624                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7907712                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26305472                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7909632                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26243                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25982                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25968                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25688                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25576                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25569                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25629                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25342                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25591                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25697                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25920                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25515                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26076                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25417                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25094                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25609                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8586                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8089                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7939                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7426                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7272                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7413                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7547                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7156                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7533                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7641                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7810                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7729                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8256                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7847                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7516                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7798                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          69                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1910452747500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  411023                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 123588                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    316637                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     38767                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     25132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      904                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      160                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64267                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      532.249522                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     325.147595                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.887517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14293     22.24%     22.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11517     17.92%     40.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5102      7.94%     48.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2862      4.45%     52.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2222      3.46%     56.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1875      2.92%     58.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1935      3.01%     61.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1643      2.56%     64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22818     35.51%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64267                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5506                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        74.626952                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2826.578445                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5503     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5506                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5506                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.440610                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.769678                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.128904                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4988     90.59%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              40      0.73%     91.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             160      2.91%     94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              10      0.18%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               4      0.07%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              18      0.33%     94.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               5      0.09%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               6      0.11%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              35      0.64%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               4      0.07%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            137      2.49%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            15      0.27%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            13      0.24%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             3      0.05%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             8      0.15%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             3      0.05%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             5      0.09%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             3      0.05%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             1      0.02%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             5      0.09%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             9      0.16%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            10      0.18%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             9      0.16%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             8      0.15%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5506                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8133947000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15838622000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2054580000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19794.67                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38544.67                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.14                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     370641                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99565                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.56                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3573538.04                       # Average gap between requests
-system.physmem.pageHitRate                      87.97                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  228629940                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  121519695                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1470818580                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                320654160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3862397760.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             4332596790                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              252811200                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy        8421848610                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        4670504160                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy       449339904270                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             473022982485                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              247.596757                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1900281265750                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      402747000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1640746000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   1869662817000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  12162830000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8118960750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  18468996750                       # Time in different power states
-system.physmem_1.actEnergy                  230243580                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122373570                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1463121660                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                324318600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3740699040.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             4231975260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              230624160                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy        8237523150                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        4445714880                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy       449624008125                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             472652324325                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              247.402742                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1900567958250                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      356565750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1589032000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   1870929942000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN  11577456000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      7939162500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  18064939250                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.branchPred.lookups               16804357                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14368910                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           476654                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            10787243                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                4777357                       # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            44.287099                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 929095                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             33008                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5112942                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits            499455                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         4613487                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       206250                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9429395                       # DTB read hits
-system.cpu0.dtb.read_misses                     34826                       # DTB read misses
-system.cpu0.dtb.read_acv                          601                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  567385                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5710239                       # DTB write hits
-system.cpu0.dtb.write_misses                     8500                       # DTB write misses
-system.cpu0.dtb.write_acv                         413                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 185113                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15139634                       # DTB hits
-system.cpu0.dtb.data_misses                     43326                       # DTB misses
-system.cpu0.dtb.data_acv                         1014                       # DTB access violations
-system.cpu0.dtb.data_accesses                  752498                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1313411                       # ITB hits
-system.cpu0.itb.fetch_misses                     6916                       # ITB misses
-system.cpu0.itb.fetch_acv                         613                       # ITB acv
-system.cpu0.itb.fetch_accesses                1320327                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              12957                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6479                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    285646442.815249                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   440880288.422179                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6479    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value        39000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6479                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    59753794500                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       119514068                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          25767559                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      73719684                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   16804357                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6205907                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     86932839                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1362768                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                        60                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               30191                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       137457                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       417781                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          385                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8508507                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               323806                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         113967656                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.646847                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.957898                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               100279992     87.99%     87.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  883136      0.77%     88.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1879288      1.65%     90.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  773699      0.68%     91.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2621733      2.30%     93.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  582123      0.51%     93.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  690580      0.61%     94.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  840992      0.74%     95.25% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 5416113      4.75%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           113967656                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.140606                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.616829                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                20688539                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             82043348                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8777506                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1804992                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                653270                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             4633985                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                29119                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              64001211                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                84558                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                653270                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                21557209                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               55702323                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17600356                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9645124                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              8809372                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              61498566                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               199219                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2004403                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                243805                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               4929982                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           41484246                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             74256527                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        74125426                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           122370                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33821902                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 7662344                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1423361                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        232902                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12334048                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9834851                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6076556                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1449838                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          941199                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  54338035                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1857223                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 52670686                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            76725                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9465955                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      4150833                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1293033                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    113967656                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.462155                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.203590                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           92547755     81.21%     81.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9157312      8.04%     89.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3826452      3.36%     92.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2741793      2.41%     95.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2858470      2.51%     97.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1410754      1.24%     98.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             945179      0.83%     99.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             363161      0.32%     99.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             116780      0.10%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      113967656                       # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 167135     16.69%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                489044     48.84%     65.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               297041     29.67%     95.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemRead            26511      2.65%     97.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMemWrite           21568      2.15%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2539      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             36140522     68.62%     68.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               55958      0.11%     68.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              25396      0.05%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1267      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9743290     18.50%     87.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5689891     10.80%     98.08% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemRead         122252      0.23%     98.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMemWrite        110721      0.21%     98.52% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            778850      1.48%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              52670686                       # Type of FU issued
-system.cpu0.iq.rate                          0.440707                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1001299                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019011                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         219818324                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         65405263                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     50914307                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             568728                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            273845                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       257541                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              53361731                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 307715                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          607759                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1969497                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4520                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        18416                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       673256                       # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18394                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       367969                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                653270                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               52238307                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1038475                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           59749161                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           168806                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9834851                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6076556                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1644704                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 40383                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               797635                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         18416                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        191736                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       507842                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              699578                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             51971663                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9489993                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           699023                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3553903                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    15226009                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8258878                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5736016                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.434858                       # Inst execution rate
-system.cpu0.iew.wb_sent                      51356635                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     51171848                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26241416                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36276103                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.428166                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.723380                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts        9976632                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         564190                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           625296                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    112216183                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.442120                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.363987                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     94653327     84.35%     84.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      6985358      6.22%     90.57% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3782709      3.37%     93.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2004229      1.79%     95.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1568389      1.40%     97.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       570810      0.51%     97.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       418508      0.37%     98.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       451920      0.40%     98.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1780933      1.59%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    112216183                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            49613021                       # Number of instructions committed
-system.cpu0.commit.committedOps              49613021                       # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13268654                       # Number of memory references committed
-system.cpu0.commit.loads                      7865354                       # Number of loads committed
-system.cpu0.commit.membars                     192328                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7511599                       # Number of branches committed
-system.cpu0.commit.fp_insts                    248727                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 45921534                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              632359                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2886254      5.82%      5.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        32400169     65.31%     71.12% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          54625      0.11%     71.23% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.23% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         24929      0.05%     71.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     71.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1267      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        7944499     16.01%     87.30% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5299897     10.68%     97.98% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemRead       113183      0.23%     98.21% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMemWrite       109348      0.22%     98.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       778850      1.57%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         49613021                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1780933                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   169850432                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  120933247                       # The number of ROB writes
-system.cpu0.timesIdled                         478916                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5546412                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3700805346                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   46729302                       # Number of Instructions Simulated
-system.cpu0.committedOps                     46729302                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.557583                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.557583                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.390994                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.390994                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                68048969                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               37279666                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   121382                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  130068                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1658488                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                782262                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1253915                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.032819                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10656048                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1254345                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.495309                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         28054500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.032819                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988345                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988345                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          430                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          407                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.839844                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         56914873                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        56914873                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6773563                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6773563                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3523907                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3523907                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174492                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       174492                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       179921                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       179921                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10297470                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10297470                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10297470                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10297470                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1555944                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1555944                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1682220                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1682220                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        19936                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19936                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         3029                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         3029                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3238164                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3238164                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3238164                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3238164                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41483749500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  41483749500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85008982052                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  85008982052                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    398193000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    398193000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     17043500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     17043500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 126492731552                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 126492731552                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8329507                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8329507                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5206127                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5206127                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       194428                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       194428                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       182950                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       182950                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13535634                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13535634                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13535634                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13535634                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.186799                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.186799                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.323123                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.323123                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.102537                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.102537                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.016556                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.016556                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.239233                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.239233                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.239233                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.239233                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5626.774513                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5626.774513                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39063.102286                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 39063.102286                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      4473141                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2637                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           108649                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            100                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    41.170568                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    26.370000                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       737996                       # number of writebacks
-system.cpu0.dcache.writebacks::total           737996                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       553324                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       553324                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1430604                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1430604                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5325                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5325                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1983928                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1983928                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1983928                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1983928                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1002620                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1002620                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       251616                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       251616                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14611                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14611                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         3029                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         3029                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1254236                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1254236                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1254236                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1254236                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         6977                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         6977                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         9909                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         9909                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        16886                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        16886                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  31595131000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  31595131000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  13207477923                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13207477923                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    169739500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    169739500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14014500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14014500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  44802608923                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  44802608923                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  44802608923                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  44802608923                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1557264500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1557264500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1557264500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1557264500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.120370                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.120370                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.075149                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.075149                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.016556                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.016556                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092662                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.092662                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092662                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.092662                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4626.774513                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4626.774513                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           891919                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.368701                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7561136                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           892430                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.472526                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      30335024500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.368701                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994861                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994861                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          501                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          9401165                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         9401165                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7561136                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7561136                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7561136                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7561136                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7561136                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7561136                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       947367                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       947367                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       947367                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        947367                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       947367                       # number of overall misses
-system.cpu0.icache.overall_misses::total       947367                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13858743493                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13858743493                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13858743493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13858743493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13858743493                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13858743493                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8508503                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8508503                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8508503                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8508503                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8508503                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8508503                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111344                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.111344                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111344                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.111344                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111344                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.111344                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14628.695630                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14628.695630                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7760                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              263                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    29.505703                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       891919                       # number of writebacks
-system.cpu0.icache.writebacks::total           891919                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54705                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        54705                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        54705                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        54705                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        54705                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        54705                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       892662                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       892662                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       892662                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       892662                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       892662                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       892662                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12247880494                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12247880494                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12247880494                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12247880494                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12247880494                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12247880494                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.104914                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.104914                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.104914                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.104914                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.104914                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.104914                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933                       # average overall mshr miss latency
-system.cpu1.branchPred.lookups                4440494                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3820633                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           114977                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2284731                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 882766                       # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            38.637634                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 229523                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              8540                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        1232926                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            164040                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1068886                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        40452                       # Number of mispredicted indirect branches.
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2425125                       # DTB read hits
-system.cpu1.dtb.read_misses                     16040                       # DTB read misses
-system.cpu1.dtb.read_acv                           82                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  432289                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1438640                       # DTB write hits
-system.cpu1.dtb.write_misses                     3531                       # DTB write misses
-system.cpu1.dtb.write_acv                          65                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 162605                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3863765                       # DTB hits
-system.cpu1.dtb.data_misses                     19571                       # DTB misses
-system.cpu1.dtb.data_acv                          147                       # DTB access violations
-system.cpu1.dtb.data_accesses                  594894                       # DTB accesses
-system.cpu1.itb.fetch_hits                     679335                       # ITB hits
-system.cpu1.itb.fetch_misses                     3486                       # ITB misses
-system.cpu1.itb.fetch_acv                         144                       # ITB acv
-system.cpu1.itb.fetch_accesses                 682821                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5088                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2544                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    747516916.077044                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   396242813.132808                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2544    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value    975504000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2544                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON     8774063000                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                        17550671                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           7093737                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      17628277                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4440494                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1276329                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9234250                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 381282                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                         2                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               26389                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        68063                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        51076                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1982953                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                84304                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          16664213                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.057852                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.464693                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                13566532     81.41%     81.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  196080      1.18%     82.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  329765      1.98%     84.57% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  235529      1.41%     85.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  402874      2.42%     88.40% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  150126      0.90%     89.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  175137      1.05%     90.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  212228      1.27%     91.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1395942      8.38%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            16664213                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.253010                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.004422                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 5803889                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8198941                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2195429                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               282754                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                183199                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              845965                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 7619                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              14397519                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                23764                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                183199                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 5993501                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 917111                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6016357                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2289218                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              1264825                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              13624374                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3775                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                108540                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 34178                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                643759                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            9046149                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             16244839                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        16178929                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            59321                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              7078981                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1967160                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            511491                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         53621                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2283119                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2539964                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1543921                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           323106                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          168966                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  11939663                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             585885                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 11455956                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            28942                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2572399                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      1228155                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        432246                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     16664213                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.687459                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.414504                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           11970475     71.83%     71.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2021121     12.13%     83.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             863574      5.18%     89.14% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             618225      3.71%     92.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             572472      3.44%     96.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             300775      1.80%     98.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             197233      1.18%     99.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              86853      0.52%     99.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              33485      0.20%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       16664213                       # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  33486     10.24%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMisc                   0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     10.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                173880     53.16%     63.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               104341     31.90%     95.30% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemRead             7997      2.44%     97.75% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMemWrite            7375      2.25%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             4756      0.04%      0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7097834     61.96%     62.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               17086      0.15%     62.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              14002      0.12%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               2375      0.02%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMisc                 0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2506692     21.88%     84.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1424790     12.44%     96.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemRead          45041      0.39%     97.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMemWrite         43535      0.38%     97.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            299845      2.62%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              11455956                       # Type of FU issued
-system.cpu1.iq.rate                          0.652736                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     327079                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.028551                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          39706848                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         14995495                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     10932885                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             225297                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            107483                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       104737                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              11657954                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 120325                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          118525                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       552207                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         1214                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         5210                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       179004                       # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          539                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        99906                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                183199                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 564470                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               284501                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           13175740                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            58730                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2539964                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1543921                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            532175                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  7107                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               276039                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          5210                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         46730                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       149015                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              195745                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             11262138                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2450359                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           193817                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       650192                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3899095                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1684701                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1448736                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.641693                       # Inst execution rate
-system.cpu1.iew.wb_sent                      11092333                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     11037622                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5277529                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7434192                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.628900                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.709899                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        2589103                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         153639                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           170452                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     16200161                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.644352                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.619659                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     12420478     76.67%     76.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1746852     10.78%     87.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       623239      3.85%     91.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       386399      2.39%     93.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       294857      1.82%     95.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       125210      0.77%     96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       112311      0.69%     96.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       119786      0.74%     97.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       371029      2.29%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     16200161                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            10438605                       # Number of instructions committed
-system.cpu1.commit.committedOps              10438605                       # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3352674                       # Number of memory references committed
-system.cpu1.commit.loads                      1987757                       # Number of loads committed
-system.cpu1.commit.membars                      48909                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1497531                       # Number of branches committed
-system.cpu1.commit.fp_insts                    102779                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  9696003                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              163829                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       490211      4.70%      4.70% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         6213226     59.52%     64.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          16788      0.16%     64.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         13993      0.13%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     64.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          2375      0.02%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMisc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.54% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1991924     19.08%     83.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1323832     12.68%     96.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemRead        44742      0.43%     96.73% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMemWrite        41669      0.40%     97.13% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       299845      2.87%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         10438605                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               371029                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    28746473                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   26517839                       # The number of ROB writes
-system.cpu1.timesIdled                         134718                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         886458                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3803363525                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    9953144                       # Number of Instructions Simulated
-system.cpu1.committedOps                      9953144                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.763329                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.763329                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.567109                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.567109                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                14490611                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                7893529                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    58631                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   57835                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 573327                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                245000                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           130880                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          488.755319                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3056587                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           131392                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.263113                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      49534102500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   488.755319                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.954600                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.954600                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         14487576                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        14487576                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1941589                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1941589                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1026269                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1026269                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        40594                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        40594                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        37239                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        37239                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2967858                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2967858                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2967858                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2967858                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       240679                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       240679                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       291916                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       291916                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5260                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         5260                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3088                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         3088                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       532595                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        532595                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       532595                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       532595                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3354943500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3354943500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  12208160588                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  12208160588                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     53604000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     53604000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     17137500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     17137500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  15563104088                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  15563104088                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  15563104088                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  15563104088                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2182268                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2182268                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1318185                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1318185                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        45854                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        45854                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        40327                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        40327                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3500453                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3500453                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3500453                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3500453                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.110288                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.110288                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.221453                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.221453                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.114712                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.114712                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.076574                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.076574                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.152150                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.152150                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.152150                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.152150                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5549.708549                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5549.708549                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 29221.273365                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 29221.273365                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       720106                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          464                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            24866                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets             14                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    28.959463                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    33.142857                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks        84401                       # number of writebacks
-system.cpu1.dcache.writebacks::total            84401                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       147677                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       147677                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       243516                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       243516                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          792                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          792                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       391193                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       391193                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       391193                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       391193                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        93002                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        93002                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        48400                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        48400                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4468                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4468                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3088                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         3088                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       141402                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       141402                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       141402                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       141402                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          218                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total          218                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3156                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3156                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3374                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3374                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1257789500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1257789500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1961692747                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1961692747                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     39632000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     39632000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     14049500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     14049500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3219482247                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3219482247                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3219482247                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3219482247                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     41842500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     41842500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     41842500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total     41842500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042617                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042617                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036717                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036717                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.097440                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.097440                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.076574                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.076574                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.040395                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.040395                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.040395                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.040395                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8870.188004                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8870.188004                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4549.708549                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4549.708549                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           256309                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          470.814625                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1714023                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           256821                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             6.673999                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1883968823500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.814625                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919560                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.919560                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          2239848                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         2239848                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1714023                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1714023                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1714023                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1714023                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1714023                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1714023                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       268930                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       268930                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       268930                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        268930                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       268930                       # number of overall misses
-system.cpu1.icache.overall_misses::total       268930                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3748012499                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   3748012499                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   3748012499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   3748012499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   3748012499                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   3748012499                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1982953                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1982953                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1982953                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1982953                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1982953                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1982953                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.135621                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.135621                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.135621                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.135621                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.135621                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.135621                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13936.758632                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13936.758632                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          558                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               46                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.130435                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       256309                       # number of writebacks
-system.cpu1.icache.writebacks::total           256309                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12035                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        12035                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        12035                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        12035                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        12035                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        12035                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       256895                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       256895                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       256895                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       256895                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       256895                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       256895                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3358325499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3358325499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3358325499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3358325499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3358325499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3358325499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.129552                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.129552                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.129552                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.129552                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.129552                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.129552                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402                       # average overall mshr miss latency
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7374                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7374                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54617                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              54617                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11920                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40520                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123982                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47680                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        73906                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2735562                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             12368500                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               820500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              176500                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14153500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2825500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6058000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               90000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216256520                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27455000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41958000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.514549                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1714263350000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.514549                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.032159                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.032159                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
-system.iocache.tags.data_accesses              375579                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41731                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
-system.iocache.overall_misses::total            41731                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22652883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22652883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4915863637                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4915863637                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4938516520                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4938516520                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4938516520                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4938516520                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41731                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41731                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126552.418994                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118306.306243                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118341.676931                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118341.676931                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           695                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs   173.750000                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          179                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          179                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41731                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41731                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41731                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41731                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13702883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13702883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2835827584                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2835827584                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2849530467                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2849530467                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2849530467                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2849530467                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68283.301790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68283.301790                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   345895                       # number of replacements
-system.l2c.tags.tagsinuse                65423.250509                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4330734                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   411417                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.526386                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               6416604000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     292.398395                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5320.578215                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    58825.194930                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      208.100344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      776.978626                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.004462                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081186                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.897601                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003175                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.011856                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998280                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1663                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1868                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5665                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56191                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38351741                       # Number of tag accesses
-system.l2c.tags.data_accesses                38351741                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       822397                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          822397                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       872029                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          872029                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            2840                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1502                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                4342                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           501                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           466                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               967                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           145832                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            30945                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               176777                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        879111                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        254952                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1134063                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       723239                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        83990                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           807229                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              879111                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              869071                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              254952                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              114935                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2118069                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             879111                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             869071                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             254952                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             114935                       # number of overall hits
-system.l2c.overall_hits::total                2118069                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data             7                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data             5                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         109607                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          12062                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             121669                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        13385                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1902                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15287                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       272541                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         1968                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         274509                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             13385                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            382148                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1902                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             14030                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411465                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13385                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           382148                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1902                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            14030                       # number of overall misses
-system.l2c.overall_misses::total               411465                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data       361500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       116000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       477500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  11326788500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1531540500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12858329000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1345659000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    188021500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1533680500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  22177607000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    225042000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  22402649000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1345659000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  33504395500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    188021500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1756582500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     36794658500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1345659000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  33504395500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    188021500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1756582500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    36794658500                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       822397                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       822397                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       872029                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       872029                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2847                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1507                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4354                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          501                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          467                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           968                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       255439                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        43007                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           298446                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       892496                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       256854                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1149350                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       995780                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        85958                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1081738                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          892496                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1251219                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          256854                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          128965                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2529534                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         892496                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1251219                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         256854                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         128965                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2529534                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.002459                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.003318                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.002756                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.002141                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.001033                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.429093                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.280466                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.407675                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014997                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007405                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013301                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.273696                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.022895                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.253767                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014997                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.305421                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007405                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.108789                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.162664                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014997                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.305421                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007405                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.108789                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.162664                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 51642.857143                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        23200                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 39791.666667                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103340.010218                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126972.351186                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 105682.869096                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100534.852447                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 98854.626709                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 100325.799699                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81373.470414                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 114350.609756                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 81609.888929                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 100534.852447                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 87673.873735                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 98854.626709                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 125201.888810                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 89423.543922                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 100534.852447                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 87673.873735                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 98854.626709                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 125201.888810                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 89423.543922                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               82068                       # number of writebacks
-system.l2c.writebacks::total                    82068                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           16                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           16                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            1                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data            7                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data            5                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       109607                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        12062                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        121669                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13385                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1886                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        15271                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272541                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1967                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       274508                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13385                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       382148                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1886                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        14029                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           411448                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13385                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       382148                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1886                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        14029                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          411448                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data         6977                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data          218                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         7195                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data         9909                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3156                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13065                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        16886                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3374                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        20260                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       291500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        94500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       386000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        18500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        18500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  10230718500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1410920500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  11641639000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1211809000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    167908000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1379717000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19458079003                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    205283000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  19663362003                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1211809000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  29688797503                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    167908000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1616203500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  32684718003                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1211809000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  29688797503                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    167908000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1616203500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  32684718003                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1470022500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     39117500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1509140000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1470022500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data     39117500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1509140000                       # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.002459                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.003318                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.002756                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.002141                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.001033                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.429093                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.280466                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.407675                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014997                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007343                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013287                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.273696                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.022883                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.253766                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014997                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.305421                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007343                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.108781                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.162658                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014997                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.305421                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007343                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.108781                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.162658                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        18900                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        18500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        18500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 79438.271672                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 79438.271672                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        851998                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       399673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          538                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
-system.membus.trans_dist::ReadResp             297108                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13065                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13065                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       123588                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           263109                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             6612                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           5150                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            121960                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121558                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289958                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           45                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp          134                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40520                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1179462                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           90                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1220072                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1303517                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73906                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31556864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31630770                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34289010                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            12625                       # Total snoops (count)
-system.membus.snoopTraffic                      28672                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            485492                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001421                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.037673                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  484802     99.86%     99.86% # Request fanout histogram
-system.membus.snoop_fanout::1                     690      0.14%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              485492                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36514000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1353680299                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               56000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2179395750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy            1105081                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      5103450                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2546310                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       356575                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1075                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1007                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7195                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2260935                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13065                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13065                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       904465                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1148228                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          826225                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           10843                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          6117                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          16960                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           299845                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          299845                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1149557                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1104232                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           45                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq          236                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2677077                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3814281                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       770058                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       417575                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7678991                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    114202560                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    127366412                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     32842432                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     13680230                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              288091634                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          382034                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   6794496                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          2936985                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.126280                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.332605                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2566512     87.39%     87.39% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 370085     12.60%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    367      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                     21      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2936985                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4539093837                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           303384                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1340375720                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1912124205                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         386934286                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         217615473                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500                       # Cumulative time (in ticks) in various power states
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6479                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    176756                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   62790     40.27%     40.27% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.08%     40.36% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1928      1.24%     41.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    181      0.12%     41.71% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  90883     58.29%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              155913                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    61775     49.18%     49.18% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.10%     49.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1928      1.53%     50.82% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     181      0.14%     50.96% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   61594     49.04%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               125609                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1865241808000     97.65%     97.65% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               64326000      0.00%     97.65% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              577244500      0.03%     97.68% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               87620000      0.00%     97.69% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            44188694000      2.31%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1910159692500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.983835                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.677729                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.805635                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  293      0.18%      0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.18% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.18% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3349      2.05%      2.23% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      48      0.03%      2.26% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.26% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               149358     91.35%     93.61% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   5686      3.48%     97.09% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.09% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     1      0.00%     97.09% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     8      0.00%     97.09% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4314      2.64%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 303      0.19%     99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb                     132      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                163506                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6667                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1071                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1071                      
-system.cpu0.kern.mode_good::user                 1071                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.160642                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.276816                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1908119380500     99.91%     99.91% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1686628500      0.09%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3350                       # number of times the context was actually changed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2544                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     62917                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   19565     37.60%     37.60% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1926      3.70%     41.30% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    293      0.56%     41.86% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  30256     58.14%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               52040                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    19203     47.61%     47.61% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1926      4.78%     52.39% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     293      0.73%     53.11% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   18910     46.89%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                40332                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1875855078000     98.19%     98.19% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              566007000      0.03%     98.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              141529500      0.01%     98.23% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            33893640500      1.77%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1910456255000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.981498                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.625000                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.775019                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  181      0.33%      0.33% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1228      2.25%      2.59% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       5      0.01%      2.60% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.61% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                46571     85.30%     87.91% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   3080      5.64%     93.55% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.55% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     6      0.01%     93.56% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     1      0.00%     93.57% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.57% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3249      5.95%     99.52% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 212      0.39%     99.91% # number of callpals executed
-system.cpu1.kern.callpal::imb                      48      0.09%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 54596                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1700                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                669                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2431                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                888                      
-system.cpu1.kern.mode_good::user                  669                      
-system.cpu1.kern.mode_good::idle                  219                      
-system.cpu1.kern.mode_switch_good::kernel     0.522353                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.090086                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.370000                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        5325548500      0.28%      0.28% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1057057500      0.06%      0.33% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1904073641000     99.67%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1229                       # number of times the context was actually changed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
deleted file mode 100644
index a108805..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
deleted file mode 100644
index 311af1e..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ /dev/null
@@ -1,1732 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727:0:0:0:0
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
deleted file mode 100755
index a8a3639..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
deleted file mode 100755
index dd81d33..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:44
-gem5 executing on e108600-lin, pid 28053
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1865011607500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
deleted file mode 100644
index df3a973..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ /dev/null
@@ -1,1526 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.865014                       # Number of seconds simulated
-sim_ticks                                1865014104500                       # Number of ticks simulated
-final_tick                               1865014104500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 231832                       # Simulator instruction rate (inst/s)
-host_op_rate                                   231832                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8163594872                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 339292                       # Number of bytes of host memory used
-host_seconds                                   228.46                       # Real time elapsed on the host
-sim_insts                                    52963270                       # Number of instructions simulated
-sim_ops                                      52963270                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            962304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24880000                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25843264                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       962304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          962304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7514304                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7514304                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15036                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388750                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403801                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117411                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117411                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               515977                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13340382                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               515                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13856873                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          515977                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             515977                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4029087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4029087                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4029087                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              515977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13340382                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17885960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403801                       # Number of read requests accepted
-system.physmem.writeReqs                       117411                       # Number of write requests accepted
-system.physmem.readBursts                      403801                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117411                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25836480                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7512704                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25843264                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7514304                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25442                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25616                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25500                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25612                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25113                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25182                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24743                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24567                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25026                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25298                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25283                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25011                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24384                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25424                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25804                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25690                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7803                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7588                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7778                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7603                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7231                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7190                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6745                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6418                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7146                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6920                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7197                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7005                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7878                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8018                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7903                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          61                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1865008869500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403801                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117411                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    314099                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36538                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28723                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7904                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      139                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61269                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      544.301360                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     334.095290                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.294475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13441     21.94%     21.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10649     17.38%     39.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4420      7.21%     46.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2704      4.41%     50.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2252      3.68%     54.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1833      2.99%     57.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1848      3.02%     60.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1534      2.50%     63.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22588     36.87%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61269                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5165                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        78.156438                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2937.375866                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5162     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5165                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5165                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.727202                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.973066                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       23.761118                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4630     89.64%     89.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              34      0.66%     90.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             183      3.54%     93.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               6      0.12%     93.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               3      0.06%     94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              17      0.33%     94.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              10      0.19%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               3      0.06%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              30      0.58%     95.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               4      0.08%     95.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            158      3.06%     98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            16      0.31%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            13      0.25%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             4      0.08%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             6      0.12%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             2      0.04%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             2      0.04%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             3      0.06%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             6      0.12%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             6      0.12%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             9      0.17%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             8      0.15%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             5      0.10%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5165                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7762770500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15332051750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018475000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19229.30                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37979.30                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.85                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.03                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.86                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.03                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.79                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.83                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364450                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95361                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.28                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3578215.52                       # Average gap between requests
-system.physmem.pageHitRate                      88.24                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  215406660                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  114491355                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1440673500                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                304618320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3636824880.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             4141323030                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              240547200                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy        8014976340                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        4268063520                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy       438971983965                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             461349368400                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              247.370445                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1855266278000                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      380549250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1544966000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   1826613361750                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  11114845500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      7783583250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  17576798750                       # Time in different power states
-system.physmem_1.actEnergy                  222061140                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  118024500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1441708800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                308136600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3631907760.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             4166934840                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              235115520                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy        8062896810                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        4253243040                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy       438933503490                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             461375149740                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              247.384267                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1855254817500                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      370314000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1542730000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   1826502260750                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN  11076094000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      7841044250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  17681661500                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                19565204                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16626727                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            606351                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12911299                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5422453                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             41.997734                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1125914                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              42947                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6343232                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             564019                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5779213                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       264491                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     11109232                       # DTB read hits
-system.cpu.dtb.read_misses                      50748                       # DTB read misses
-system.cpu.dtb.read_acv                           615                       # DTB read access violations
-system.cpu.dtb.read_accesses                   993788                       # DTB read accesses
-system.cpu.dtb.write_hits                     6757496                       # DTB write hits
-system.cpu.dtb.write_misses                     12693                       # DTB write misses
-system.cpu.dtb.write_acv                          420                       # DTB write access violations
-system.cpu.dtb.write_accesses                  345501                       # DTB write accesses
-system.cpu.dtb.data_hits                     17866728                       # DTB hits
-system.cpu.dtb.data_misses                      63441                       # DTB misses
-system.cpu.dtb.data_acv                          1035                       # DTB access violations
-system.cpu.dtb.data_accesses                  1339289                       # DTB accesses
-system.cpu.itb.fetch_hits                     1817930                       # ITB hits
-system.cpu.itb.fetch_misses                     10423                       # ITB misses
-system.cpu.itb.fetch_acv                          754                       # ITB acv
-system.cpu.itb.fetch_accesses                 1828353                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12882                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6441                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     279499621.875485                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    438940062.434372                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6441    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value        80500                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6441                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     64757040000                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        129520522                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           30117726                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       85842784                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19565204                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            7112386                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      91831627                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1707334                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         94                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                30324                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        206515                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       432806                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          499                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9953050                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                416768                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          123473258                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.695234                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.025215                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                107617936     87.16%     87.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1029887      0.83%     87.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2106014      1.71%     89.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   969195      0.78%     90.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2907839      2.36%     92.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   668408      0.54%     93.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   818971      0.66%     94.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1034002      0.84%     94.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6321006      5.12%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            123473258                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.151059                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.662774                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24152038                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              86201336                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  10258063                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2042752                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 819068                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              5235547                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 36008                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               74118733                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                112337                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 819068                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25161583                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                56623083                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20020475                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11228852                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               9620195                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               71027053                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                203339                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2122213                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 263594                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5326402                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            47839712                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              85552570                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         85371726                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168391                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38166163                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9673541                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1731851                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         279206                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13863805                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             11669742                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7218714                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1729922                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1107908                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   62661067                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2212545                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  60426230                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             90696                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11910337                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      5399466                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1551308                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     123473258                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.489387                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.234720                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            98959132     80.15%     80.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10414953      8.43%     88.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4418122      3.58%     92.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3174360      2.57%     94.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3248671      2.63%     97.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1596633      1.29%     98.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1092968      0.89%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              431056      0.35%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              137363      0.11%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       123473258                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  204093     16.54%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc                    0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 604376     48.98%     65.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                366984     29.74%     95.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead             31970      2.59%     97.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite            26536      2.15%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7279      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              40835249     67.58%     67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                62139      0.10%     67.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38557      0.06%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             11506324     19.04%     86.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6726484     11.13%     97.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead          156184      0.26%     98.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite         141292      0.23%     98.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949086      1.57%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               60426230                       # Type of FU issued
-system.cpu.iq.rate                           0.466538                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1233959                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.020421                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          244910582                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          76445733                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     58177679                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              739790                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             359586                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       336759                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               61254735                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  398175                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           690768                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2579745                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4605                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        21941                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       842112                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18009                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        459546                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 819068                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                52732826                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1310921                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            68860028                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            210874                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              11669742                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              7218714                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1962223                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  46667                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1061185                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          21941                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         239076                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       633747                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               872823                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              59548676                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              11192398                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            877553                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3986416                       # number of nop insts executed
-system.cpu.iew.exec_refs                     17982691                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  9367788                       # Number of branches executed
-system.cpu.iew.exec_stores                    6790293                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.459762                       # Inst execution rate
-system.cpu.iew.wb_sent                       58762094                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      58514438                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  29700638                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  41179298                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.451777                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.721252                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        12514858                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661237                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            782772                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    121281996                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.462997                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.395862                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    101434078     83.63%     83.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7974018      6.57%     90.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4186796      3.45%     93.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2256770      1.86%     95.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1754187      1.45%     96.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       639315      0.53%     97.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       479528      0.40%     97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       513600      0.42%     98.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2043704      1.69%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    121281996                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56153243                       # Number of instructions committed
-system.cpu.commit.committedOps               56153243                       # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15466599                       # Number of memory references committed
-system.cpu.commit.loads                       9089997                       # Number of loads committed
-system.cpu.commit.membars                      226363                       # Number of memory barriers committed
-system.cpu.commit.branches                    8438860                       # Number of branches committed
-system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52003390                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740372                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3197246      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36205593     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60678      0.11%     70.28% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9171764     16.33%     86.69% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6244492     11.12%     97.81% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead       144596      0.26%     98.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite       138067      0.25%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949086      1.69%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56153243                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2043704                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    187656858                       # The number of ROB reads
-system.cpu.rob.rob_writes                   139533948                       # The number of ROB writes
-system.cpu.timesIdled                          550447                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6047264                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3600507688                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52963270                       # Number of Instructions Simulated
-system.cpu.committedOps                      52963270                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.445478                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.445478                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.408918                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.408918                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 77682847                       # number of integer regfile reads
-system.cpu.int_regfile_writes                42491451                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166573                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   175777                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2001872                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939479                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1405824                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994108                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            12609719                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1406336                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.966363                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          28054500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994108                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          414                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          67057386                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         67057386                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      8001397                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         8001397                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4179263                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4179263                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       213150                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       213150                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215702                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215702                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      12180660                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         12180660                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     12180660                       # number of overall hits
-system.cpu.dcache.overall_hits::total        12180660                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1813374                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1813374                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1966870                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1966870                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22944                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22944                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           62                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           62                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3780244                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3780244                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3780244                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3780244                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  45111482000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  45111482000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  92228872060                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  92228872060                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    421566000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    421566000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       865000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       865000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 137340354060                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 137340354060                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 137340354060                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 137340354060                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9814771                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9814771                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6146133                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6146133                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       236094                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       236094                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215764                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215764                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15960904                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15960904                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15960904                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15960904                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184760                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.184760                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320017                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.320017                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.097182                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.097182                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000287                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000287                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.236844                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.236844                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.236844                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.236844                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24877.097609                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24877.097609                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46891.188569                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46891.188569                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18373.692469                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18373.692469                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13951.612903                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13951.612903                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36331.081819                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36331.081819                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36331.081819                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36331.081819                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      4936405                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         4609                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            132646                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              30                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.214880                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   153.633333                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       843338                       # number of writebacks
-system.cpu.dcache.writebacks::total            843338                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       712674                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       712674                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1677487                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1677487                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         6576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2390161                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2390161                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2390161                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2390161                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1100700                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1100700                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289383                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289383                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16368                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16368                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           62                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           62                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1390083                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1390083                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1390083                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1390083                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33019179500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33019179500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14332081529                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14332081529                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205108500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205108500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       803000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       803000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47351261029                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  47351261029                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47351261029                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  47351261029                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1535277500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1535277500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1535277500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1535277500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.112147                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.112147                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047084                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047084                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.069328                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.069328                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000287                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000287                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.087093                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.087093                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.087093                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.087093                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1070370                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.026702                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8813001                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1070878                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.229697                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       30284278500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.026702                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994193                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994193                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          11024191                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         11024191                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst      8813002                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8813002                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8813002                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8813002                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8813002                       # number of overall hits
-system.cpu.icache.overall_hits::total         8813002                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1140039                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1140039                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1140039                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1140039                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1140039                       # number of overall misses
-system.cpu.icache.overall_misses::total       1140039                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16263731493                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16263731493                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16263731493                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16263731493                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16263731493                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16263731493                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9953041                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9953041                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9953041                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9953041                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9953041                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9953041                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.114542                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.114542                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.114542                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.114542                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.114542                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.114542                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14265.943089                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14265.943089                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14265.943089                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14265.943089                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14265.943089                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14265.943089                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         8433                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               292                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.880137                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1070370                       # number of writebacks
-system.cpu.icache.writebacks::total           1070370                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68889                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        68889                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        68889                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        68889                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        68889                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        68889                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1071150                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1071150                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1071150                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1071150                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1071150                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1071150                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14349436996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14349436996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14349436996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14349436996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14349436996                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14349436996                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.107620                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.107620                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.107620                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.107620                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.107620                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.107620                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13396.290899                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13396.290899                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13396.290899                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13396.290899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13396.290899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13396.290899                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           338611                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65420.352754                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4547118                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404133                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            11.251538                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6414124000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   256.173828                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5307.615094                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 59856.563832                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.003909                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080988                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.913339                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998235                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          896                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          439                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5606                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        58575                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40018321                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40018321                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       843338                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       843338                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1069837                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1069837                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           60                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           60                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           62                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           62                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       185066                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       185066                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1055887                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1055887                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       832119                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       832119                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1055887                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1017185                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2073072                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1055887                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1017185                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2073072                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           10                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           10                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       114704                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       114704                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15037                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        15037                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       274496                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       274496                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15037                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389200                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404237                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15037                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389200                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404237                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       448000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       448000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12012512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  12012512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1519237500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1519237500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  22383517000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  22383517000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1519237500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  34396029000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  35915266500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1519237500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  34396029000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  35915266500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       843338                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       843338                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1069837                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1069837                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           70                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           70                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           62                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           62                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       299770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       299770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1070924                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1070924                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1106615                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1106615                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1070924                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1406385                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2477309                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1070924                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1406385                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2477309                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.142857                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.142857                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382640                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.382640                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014041                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014041                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248050                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248050                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014041                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.276738                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.163176                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014041                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.276738                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.163176                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        44800                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        44800                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104726.182173                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104726.182173                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101033.284565                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101033.284565                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81544.055287                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81544.055287                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101033.284565                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88376.230730                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 88847.053832                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101033.284565                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88376.230730                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 88847.053832                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        75899                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75899                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114704                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       114704                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15037                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15037                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274496                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274496                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15037                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389200                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404237                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15037                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389200                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404237                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       348000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       348000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10865472000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10865472000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1368867500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1368867500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19644703500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19644703500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1368867500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  30510175500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  31879043000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1368867500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  30510175500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  31879043000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1448637000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1448637000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1448637000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1448637000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.142857                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.142857                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382640                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382640                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014041                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014041                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248050                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248050                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276738                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.163176                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014041                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276738                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.163176                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        34800                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        34800                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4953861                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2476312                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4344                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          953                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          953                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2184804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       919237                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1070370                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       825198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           70                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           62                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       299770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       299770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1071150                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           47                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq          236                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp            2                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3212444                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4252074                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7464518                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137042816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144033404                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          281076220                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      339392                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4881984                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2833204                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001872                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.043223                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2827901     99.81%     99.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5303      0.19%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2833204                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4403702500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       292883                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1607637172                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2121526099                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51151                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51151                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5054                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33058                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116508                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20216                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44156                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705764                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5360000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               815500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              180500                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14072500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2178500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6063000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               93500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216225034                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23459000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.265440                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1714255689000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.265440                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.079090                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.079090                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21944883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21944883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4931807151                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4931807151                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4953752034                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4953752034                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4953752034                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4953752034                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126849.034682                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118690.006522                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118723.835446                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118723.835446                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs          1219                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   12                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs   101.583333                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13294883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13294883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2851781783                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2851781783                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2865076666                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2865076666                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2865076666                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2865076666                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68665.707993                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68665.707993                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        825536                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       380380                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          527                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296589                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9599                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117411                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262092                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              137                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            114577                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           114577                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289706                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           47                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp          124                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33058                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           94                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1178956                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1262381                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44156                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30699840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30743996                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33401724                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              562                       # Total snoops (count)
-system.membus.snoopTraffic                      27840                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            462501                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001464                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.038231                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  461824     99.85%     99.85% # Request fanout histogram
-system.membus.snoop_fanout::1                     677      0.15%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              462501                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28785000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1313532070                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               60000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2137876500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy            1057021                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500                       # Cumulative time (in ticks) in various power states
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6441                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211020                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74665     40.97%     40.97% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1881      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105573     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182250                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73298     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1881      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73298     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148608                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1819143935000     97.54%     97.54% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                67422000      0.00%     97.54% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               565966500      0.03%     97.57% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             45235960500      2.43%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1865013284000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694287                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815407                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175131     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6785      3.53%     96.97% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5106      2.66%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191978                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326098                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393971                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29665976500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2757716000      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1832589583500     98.26%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
deleted file mode 100644
index b49f55c..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY
+++ /dev/null
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
deleted file mode 100644
index 55e1410..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ /dev/null
@@ -1,1442 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu0.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu1.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu0
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
deleted file mode 100755
index 25e6a47..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
deleted file mode 100755
index a53acdd..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ /dev/null
@@ -1,16 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:26
-gem5 executing on e108600-lin, pid 39599
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 97861500
-Exiting @ tick 1869357999000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
deleted file mode 100644
index 54bff4f..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ /dev/null
@@ -1,1010 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.869358                       # Number of seconds simulated
-sim_ticks                                1869358054000                       # Number of ticks simulated
-final_tick                               1869358054000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2951277                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2951276                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            84876880961                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 336132                       # Number of bytes of host memory used
-host_seconds                                    22.02                       # Real time elapsed on the host
-sim_insts                                    64999904                       # Number of instructions simulated
-sim_ops                                      64999904                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           758272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         66535744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           106112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           766400                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68167488                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       758272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       106112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          864384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7837888                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7837888                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11848                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1039621                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1658                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11975                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1065117                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122467                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122467                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              405632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35592830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56764                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              409980                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36465720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         405632                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56764                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             462396                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4192823                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4192823                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4192823                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             405632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35592830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             409980                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40658544                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7758808                       # DTB read hits
-system.cpu0.dtb.read_misses                      7155                       # DTB read misses
-system.cpu0.dtb.read_acv                          152                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  531148                       # DTB read accesses
-system.cpu0.dtb.write_hits                    4740251                       # DTB write hits
-system.cpu0.dtb.write_misses                      732                       # DTB write misses
-system.cpu0.dtb.write_acv                         102                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 201714                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12499059                       # DTB hits
-system.cpu0.dtb.data_misses                      7887                       # DTB misses
-system.cpu0.dtb.data_acv                          254                       # DTB access violations
-system.cpu0.dtb.data_accesses                  732862                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3525726                       # ITB hits
-system.cpu0.itb.fetch_misses                     3572                       # ITB misses
-system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_accesses                3529298                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              13588                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6794                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    271506712.952752                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   434955679.637595                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6794    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value        21000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6794                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    24741446199                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      3738722903                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6794                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    150435                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   51398     40.00%     40.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    243      0.19%     40.19% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1907      1.48%     41.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    514      0.40%     42.07% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  74446     57.93%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              128508                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    51050     48.97%     48.97% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     243      0.23%     49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1907      1.83%     51.03% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     514      0.49%     51.52% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   50536     48.48%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               104250                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1853222787000     99.14%     99.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22               82001000      0.00%     99.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               57621500      0.00%     99.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            15975327000      0.85%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1869357846500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.993229                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.678828                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811234                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  616      0.45%      0.45% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.45% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.46% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.46% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 2743      2.02%      2.47% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      39      0.03%      2.50% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.01%      2.51% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               121668     89.51%     92.02% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6149      4.52%     96.54% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.54% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.54% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.01%     96.55% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.55% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4175      3.07%     99.62% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 369      0.27%     99.89% # number of callpals executed
-system.cpu0.kern.callpal::imb                     146      0.11%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                135929                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6593                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1172                      
-system.cpu0.kern.mode_good::user                 1173                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.177764                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.301957                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1868349218500     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1008627000      0.05%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2744                       # number of times the context was actually changed
-system.cpu0.committedInsts                   49477745                       # Number of instructions committed
-system.cpu0.committedOps                     49477745                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             46201705                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                197598                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1124633                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6043603                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    46201705                       # number of integer instructions
-system.cpu0.num_fp_insts                       197598                       # number of float instructions
-system.cpu0.num_int_register_reads           64003225                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          34834421                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               97440                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              98967                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12536107                       # number of memory refs
-system.cpu0.num_load_insts                    7783754                       # Number of load instructions
-system.cpu0.num_store_insts                   4752353                       # Number of store instructions
-system.cpu0.num_idle_cycles              3689239920.666412                       # Number of idle cycles
-system.cpu0.num_busy_cycles              49482982.333588                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.013235                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.986765                       # Percentage of idle cycles
-system.cpu0.Branches                          7530826                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2589816      5.23%      5.23% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 33436017     67.57%     72.80% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50540      0.10%     72.90% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     72.90% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  27840      0.06%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   2233      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatMisc                     0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7859946     15.88%     88.85% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4676411      9.45%     98.30% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead              85644      0.17%     98.47% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite             81881      0.17%     98.63% # Class of executed instruction
-system.cpu0.op_class::IprAccess                675558      1.37%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  49485886                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1781367                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.187332                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10705767                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1781879                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             6.008134                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187332                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988647                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988647                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          446                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51822038                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51822038                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6068885                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6068885                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4360096                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4360096                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       127592                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       127592                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       132871                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       132871                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10428981                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10428981                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10428981                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10428981                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1560065                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1560065                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       236527                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       236527                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12626                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        12626                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         6899                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         6899                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1796592                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1796592                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1796592                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1796592                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7628950                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7628950                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4596623                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4596623                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       140218                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       140218                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       139770                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       139770                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12225573                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12225573                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12225573                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12225573                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.204493                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.204493                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051457                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051457                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.090046                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090046                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049360                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.049360                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.146954                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146954                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.146954                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146954                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       633925                       # number of writebacks
-system.cpu0.dcache.writebacks::total           633925                       # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           618292                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.240644                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           48866947                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           618804                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            78.969992                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9786048500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.240644                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998517                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998517                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         50104825                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        50104825                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     48866947                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       48866947                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     48866947                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        48866947                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     48866947                       # number of overall hits
-system.cpu0.icache.overall_hits::total       48866947                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       618939                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       618939                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       618939                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        618939                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       618939                       # number of overall misses
-system.cpu0.icache.overall_misses::total       618939                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     49485886                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     49485886                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     49485886                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     49485886                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     49485886                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     49485886                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012507                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.012507                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012507                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.012507                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012507                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.012507                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       618292                       # number of writebacks
-system.cpu0.icache.writebacks::total           618292                       # number of writebacks
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2831559                       # DTB read hits
-system.cpu1.dtb.read_misses                      3191                       # DTB read misses
-system.cpu1.dtb.read_acv                           58                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  198160                       # DTB read accesses
-system.cpu1.dtb.write_hits                    2101673                       # DTB write hits
-system.cpu1.dtb.write_misses                      412                       # DTB write misses
-system.cpu1.dtb.write_acv                          55                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  90619                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4933232                       # DTB hits
-system.cpu1.dtb.data_misses                      3603                       # DTB misses
-system.cpu1.dtb.data_acv                          113                       # DTB access violations
-system.cpu1.dtb.data_accesses                  288779                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1950883                       # ITB hits
-system.cpu1.itb.fetch_misses                     1451                       # ITB misses
-system.cpu1.itb.fetch_acv                          57                       # ITB acv
-system.cpu1.itb.fetch_accesses                1952334                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5407                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2704                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    688459953.587278                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   437290552.872181                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2704    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value    976035500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2704                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON     7762339500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      3738296719                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2704                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     92290                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   31964     39.34%     39.34% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1906      2.35%     41.68% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    616      0.76%     42.44% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  46769     57.56%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               81255                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    30935     48.51%     48.51% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1906      2.99%     51.49% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     616      0.97%     52.46% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   30319     47.54%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                63776                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1856123556500     99.30%     99.30% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22               81958000      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               70736500      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            12870743500      0.69%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1869146994500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.967808                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.648271                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.784887                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  514      0.61%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2506      2.96%      3.58% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      14      0.02%      3.59% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.60% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                74617     88.26%     91.86% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2575      3.05%     94.91% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.91% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.00%     94.91% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.00%     94.91% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.92% # number of callpals executed
-system.cpu1.kern.callpal::rti                    4115      4.87%     99.79% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 146      0.17%     99.96% # number of callpals executed
-system.cpu1.kern.callpal::imb                      34      0.04%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 84542                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2548                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                564                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               3056                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel               1106                      
-system.cpu1.kern.mode_good::user                  564                      
-system.cpu1.kern.mode_good::idle                  542                      
-system.cpu1.kern.mode_switch_good::kernel     0.434066                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.177356                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.358625                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        5986368000      0.32%      0.32% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           456602000      0.02%      0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1862102446500     99.66%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2507                       # number of times the context was actually changed
-system.cpu1.committedInsts                   15522159                       # Number of instructions committed
-system.cpu1.committedOps                     15522159                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             14295544                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                198941                       # Number of float alu accesses
-system.cpu1.num_func_calls                     493140                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1540068                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    14295544                       # number of integer instructions
-system.cpu1.num_fp_insts                       198941                       # number of float instructions
-system.cpu1.num_int_register_reads           19514289                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          10457600                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              101734                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             104129                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4961786                       # number of memory refs
-system.cpu1.num_load_insts                    2849090                       # Number of load instructions
-system.cpu1.num_store_insts                   2112696                       # Number of store instructions
-system.cpu1.num_idle_cycles              3722773781.474732                       # Number of idle cycles
-system.cpu1.num_busy_cycles              15522937.525268                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.004152                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.995848                       # Percentage of idle cycles
-system.cpu1.Branches                          2214163                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               856043      5.51%      5.51% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  9156766     58.98%     64.49% # Class of executed instruction
-system.cpu1.op_class::IntMult                   25065      0.16%     64.65% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.65% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  12426      0.08%     64.73% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.73% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.73% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.73% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc                  0      0.00%     64.73% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1409      0.01%     64.74% # Class of executed instruction
-system.cpu1.op_class::FloatMisc                     0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2842559     18.31%     83.05% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2023248     13.03%     96.08% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead              94457      0.61%     96.69% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite             90649      0.58%     97.27% # Class of executed instruction
-system.cpu1.op_class::IprAccess                423253      2.73%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  15525875                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           201757                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          497.601957                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4718401                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           202065                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.350907                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      15869420000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.601957                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971879                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.971879                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.601562                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         20020608                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        20020608                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2632688                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2632688                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1954647                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1954647                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        61098                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        61098                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        64211                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        64211                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      4587335                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         4587335                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      4587335                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        4587335                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       140885                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       140885                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        78313                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        78313                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11000                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11000                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         7304                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         7304                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       219198                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        219198                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       219198                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       219198                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2773573                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2773573                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2032960                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2032960                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72098                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        72098                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        71515                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        71515                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4806533                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4806533                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4806533                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4806533                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050795                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.050795                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.038522                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.038522                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152570                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152570                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.102132                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.102132                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.045604                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.045604                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.045604                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.045604                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       144832                       # number of writebacks
-system.cpu1.dcache.writebacks::total           144832                       # number of writebacks
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           380647                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          453.133721                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           15144687                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           381159                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.733253                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1859777228500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133721                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.885027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         15907063                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        15907063                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     15144687                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       15144687                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     15144687                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        15144687                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     15144687                       # number of overall hits
-system.cpu1.icache.overall_hits::total       15144687                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       381188                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       381188                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       381188                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        381188                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       381188                       # number of overall misses
-system.cpu1.icache.overall_misses::total       381188                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     15525875                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     15525875                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     15525875                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     15525875                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     15525875                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     15525875                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024552                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024552                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024552                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024552                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024552                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024552                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       380647                       # number of writebacks
-system.cpu1.icache.writebacks::total           380647                       # number of writebacks
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7628                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7628                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              56140                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14686                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1014                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18036                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        44074                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  127536                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        58744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2749                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9018                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2747818                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.434096                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1685787164517                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.434096                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.027131                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.027131                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
-system.iocache.tags.data_accesses              375579                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41731                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
-system.iocache.overall_misses::total            41731                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41731                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41731                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   999962                       # number of replacements
-system.l2c.tags.tagsinuse                65520.418445                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4560627                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1065470                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.280390                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                618103500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     304.654012                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4865.757484                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    58473.870624                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      175.171542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1700.964784                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.004649                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074246                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.892240                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002673                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.025955                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.999762                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65508                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          674                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2411                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2462                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9328                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        50633                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999573                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 46077150                       # Number of tag accesses
-system.l2c.tags.data_accesses                46077150                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       778757                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          778757                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       721479                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          721479                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            3102                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            2744                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                5846                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          1187                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1121                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              2308                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           111978                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            56627                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               168605                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        607070                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        379530                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            986600                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       626251                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       128790                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           755041                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              607070                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              738229                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              379530                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              185417                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1910246                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             607070                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             738229                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             379530                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             185417                       # number of overall hits
-system.l2c.overall_hits::total                1910246                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data             4                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data             2                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 6                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113307                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          11044                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             124351                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        11848                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1658                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           13506                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       926616                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         1036                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         927652                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             11848                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data           1039923                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1658                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             12080                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1065509                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11848                       # number of overall misses
-system.l2c.overall_misses::cpu0.data          1039923                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1658                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            12080                       # number of overall misses
-system.l2c.overall_misses::total              1065509                       # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks       778757                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       778757                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       721479                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       721479                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3106                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2746                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5852                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1187                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1122                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2309                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       225285                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        67671                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292956                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       618918                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       381188                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1000106                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      1552867                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       129826                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1682693                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          618918                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1778152                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          381188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          197497                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2975755                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         618918                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1778152                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         381188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         197497                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2975755                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.001288                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.000728                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.001025                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.000891                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.000433                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.502950                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.163201                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.424470                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.019143                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004350                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013505                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.596713                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.007980                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.551290                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.019143                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.584834                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004350                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.061165                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.358063                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.019143                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.584834                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004350                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.061165                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.358063                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               80947                       # number of writebacks
-system.l2c.writebacks::total                    80947                       # number of writebacks
-system.membus.snoop_filter.tot_requests       2174394                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1068314                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          544                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7449                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948786                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14588                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       122467                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           918018                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            13880                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11895                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             135                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            125245                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           124223                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        941337                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        44074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3156480                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3200554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125161                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       125161                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3325715                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73364992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     73451154                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2668736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2668736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                76119890                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2196431                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.000560                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.023658                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2195201     99.94%     99.94% # Request fanout histogram
-system.membus.snoop_fanout::1                    1230      0.06%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2196431                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      6035809                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      3010644                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       386637                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1627                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1537                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops           90                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7449                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2732152                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14588                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       778757                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       998939                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1204367                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           19598                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         14203                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          33801                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295242                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295242                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1000127                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1724576                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1856170                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5450061                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1143023                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       684375                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               9133629                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     79182784                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155817595                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     48757440                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23377367                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              307135186                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1001076                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   5203008                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          7058756                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.107956                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.310579                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                6297275     89.21%     89.21% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 760929     10.78%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    550      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7058756                       # Request fanout histogram
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
deleted file mode 100644
index 6129834..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
deleted file mode 100644
index 4ec6fe9..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ /dev/null
@@ -1,1278 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
deleted file mode 100755
index 8aa0366..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
deleted file mode 100755
index 9ca182d..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39612
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1829331993500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
deleted file mode 100644
index 50044fb..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ /dev/null
@@ -1,656 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332014500                       # Number of ticks simulated
-final_tick                               1829332014500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3082632                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3082630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            93925630949                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 334080                       # Number of bytes of host memory used
-host_seconds                                    19.48                       # Real time elapsed on the host
-sim_insts                                    60038469                       # Number of instructions simulated
-sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66835072                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             67686528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7415744                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7415744                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044298                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1057602                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115871                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115871                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               464922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36535233                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37000680                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          464922                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464922                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4053799                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4053799                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4053799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              464922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36535233                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41054479                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710423                       # DTB read hits
-system.cpu.dtb.read_misses                      10329                       # DTB read misses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
-system.cpu.dtb.write_hits                     6352496                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062919                       # DTB hits
-system.cpu.dtb.data_misses                      11471                       # DTB misses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974637                       # ITB hits
-system.cpu.itb.fetch_misses                      5006                       # ITB misses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12714                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6357                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     283043478.877143                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    441371901.217911                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6357    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value       386000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6357                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     30024619278                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       3658670387                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811929148500     99.05%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829331807000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192179                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1737                      
-system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801033420500     98.45%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.cpu.committedInsts                    60038469                       # Number of instructions committed
-system.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913692                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110791                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913692                       # number of integer instructions
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76954245                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740352                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115703                       # number of memory refs
-system.cpu.num_load_insts                     9747509                       # Number of load instructions
-system.cpu.num_store_insts                    6368194                       # Number of store instructions
-system.cpu.num_idle_cycles               3598621044.088899                       # Number of idle cycles
-system.cpu.num_busy_cycles               60049342.911101                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
-system.cpu.Branches                           9064428                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3199100      5.33%      5.33% # Class of executed instruction
-system.cpu.op_class::IntAlu                  39448406     65.69%     71.02% # Class of executed instruction
-system.cpu.op_class::IntMult                    60677      0.10%     71.12% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     71.18% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     71.18% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     71.18% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     71.18% # Class of executed instruction
-system.cpu.op_class::FloatDiv                    3636      0.01%     71.19% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::MemRead                  9830448     16.37%     87.56% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6236007     10.38%     97.95% # Class of executed instruction
-system.cpu.op_class::FloatMemRead              144629      0.24%     98.19% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite             138108      0.23%     98.42% # Class of executed instruction
-system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   60050307                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           2042708                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14038419                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2043220                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              6.870733                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          66369781                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         66369781                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7807771                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807771                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848209                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848209                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655980                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655980                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655980                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655980                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721712                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721712                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304363                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304363                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026075                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026075                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026075                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026075                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682055                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682055                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682055                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682055                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       833476                       # number of writebacks
-system.cpu.dcache.writebacks::total            833476                       # number of writebacks
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            919605                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            59130075                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            920117                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             64.263648                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60970539                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60970539                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     59130075                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59130075                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59130075                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59130075                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59130075                       # number of overall hits
-system.cpu.icache.overall_hits::total        59130075                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920232                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920232                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920232                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920232                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920232                       # number of overall misses
-system.cpu.icache.overall_misses::total        920232                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050307                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050307                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050307                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       919605                       # number of writebacks
-system.cpu.icache.writebacks::total            919605                       # number of writebacks
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           992419                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65520.104764                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4865571                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1057941                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.599095                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   264.552906                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4852.732204                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.004037                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074047                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.921674                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          606                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3042                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6629                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55077                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         48449706                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        48449706                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       833476                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       833476                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       919353                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       919353                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187293                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187293                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811230                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       811230                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906925                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998523                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905448                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906925                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998523                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905448                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117054                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117054                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13289                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        13289                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       927644                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       927644                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13289                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044698                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1057987                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13289                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044698                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1057987                       # number of overall misses
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       833476                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       833476                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       919353                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       919353                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1738874                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920214                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043221                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2963435                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920214                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043221                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2963435                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.250000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384607                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384607                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014441                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014441                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533474                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533474                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014441                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511300                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.357014                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014441                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511300                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.357014                       # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74359                       # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests      5925782                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962349                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2223                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1449                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2666290                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       833476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       919605                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1209232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304347                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304347                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       920232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738874                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760069                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163226                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8923295                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154734                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          301904302                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      993442                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4779456                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      6936088                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000848                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.029106                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            6930207     99.92%     99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5881      0.08%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6936088                       # Request fanout histogram
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51390                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41686                       # number of replacements
-system.iocache.tags.tagsinuse                1.225570                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1685780588017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.225570                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
-system.iocache.tags.data_accesses              375534                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.membus.snoop_filter.tot_requests       2132776                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1034104                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7184                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948291                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115871                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           917188                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              133                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             133                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116925                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116925                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        941107                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3107355                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3141399                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125138                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       125138                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3266537                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72461888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72508014                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2667904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2667904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                75175918                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2149798                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.000529                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.023002                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2148660     99.95%     99.95% # Request fanout histogram
-system.membus.snoop_fanout::1                    1138      0.05%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2149798                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
deleted file mode 100644
index f17158b..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
deleted file mode 100644
index 7dde96a..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ /dev/null
@@ -1,1499 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727:0:0:0:0
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu0.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu1.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu0
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
deleted file mode 100755
index 9acbae0..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
deleted file mode 100755
index d5fb9a1..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ /dev/null
@@ -1,16 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:44
-gem5 executing on e108600-lin, pid 28056
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 752919000
-Exiting @ tick 1966741627000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
deleted file mode 100644
index 5f20e94..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ /dev/null
@@ -1,1782 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.966742                       # Number of seconds simulated
-sim_ticks                                1966742176000                       # Number of ticks simulated
-final_tick                               1966742176000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1742915                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1742915                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            56229643103                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 335876                       # Number of bytes of host memory used
-host_seconds                                    34.98                       # Real time elapsed on the host
-sim_insts                                    60961842                       # Number of instructions simulated
-sim_ops                                      60961842                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           796800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24828736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            62272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           430784                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26119552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       796800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        62272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          859072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7774400                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7774400                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             12450                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            387949                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               973                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              6731                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                408118                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          121475                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121475                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              405137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12624296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               31663                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              219034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13280618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         405137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          31663                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             436800                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3952933                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3952933                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3952933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             405137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12624296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              31663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             219034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17233551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        408118                       # Number of read requests accepted
-system.physmem.writeReqs                       121475                       # Number of write requests accepted
-system.physmem.readBursts                      408118                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121475                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26112384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7772672                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26119552                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7774400                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25299                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25599                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25910                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25657                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25586                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25177                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26012                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25110                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25002                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25326                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25349                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25350                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25737                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25386                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25673                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25833                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7888                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7973                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7891                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7697                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7528                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7375                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8079                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7030                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7056                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7058                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7244                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7671                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7657                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7545                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7813                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7943                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          71                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1966734882500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  408118                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 121475                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407913                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      156                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65997                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      513.433277                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     309.806046                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     413.661980                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15519     23.51%     23.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12333     18.69%     42.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4691      7.11%     49.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3281      4.97%     54.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3296      4.99%     59.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1531      2.32%     61.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1650      2.50%     64.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1071      1.62%     65.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22625     34.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65997                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5403                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        75.512863                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2871.806103                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5400     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5403                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5403                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.477883                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.790649                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.259878                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4886     90.43%     90.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              27      0.50%     90.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             174      3.22%     94.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               7      0.13%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               5      0.09%     94.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              18      0.33%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              10      0.19%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               2      0.04%     94.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              26      0.48%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               6      0.11%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            152      2.81%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            23      0.43%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             4      0.07%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             3      0.06%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             4      0.07%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             5      0.09%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             2      0.04%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.02%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             1      0.02%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             5      0.09%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             7      0.13%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            10      0.19%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             7      0.13%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.06%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             6      0.11%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             4      0.07%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-343             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5403                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6253232750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13903345250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2040030000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15326.33                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34076.33                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.28                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.81                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     365871                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97586                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3713672.35                       # Average gap between requests
-system.physmem.pageHitRate                      87.53                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  236455380                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125679015                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1459059000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                320826420                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           5647926960.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5154923820                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              376838880                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy       13418648160                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        6443555040                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy       458974810065                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             492161345970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              250.241923                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1954449369000                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      631981750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2402382000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   1908243357500                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  16780134250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9257305750                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  29427014750                       # Time in different power states
-system.physmem_1.actEnergy                  234763200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  124779600                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1454103840                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                313132140                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           5778230640.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5151828720                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              364649760                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy       13829543490                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        6726228480                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy       458595076560                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             492575015880                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              250.452256                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1954420956750                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      598934250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2457676000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   1906644575500                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN  17516296750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9196775500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  30327918000                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7479524                       # DTB read hits
-system.cpu0.dtb.read_misses                      7764                       # DTB read misses
-system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  524068                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5079926                       # DTB write hits
-system.cpu0.dtb.write_misses                      909                       # DTB write misses
-system.cpu0.dtb.write_acv                         133                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 202594                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12559450                       # DTB hits
-system.cpu0.dtb.data_misses                      8673                       # DTB misses
-system.cpu0.dtb.data_acv                          343                       # DTB access violations
-system.cpu0.dtb.data_accesses                  726662                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3638587                       # ITB hits
-system.cpu0.itb.fetch_misses                     3984                       # ITB misses
-system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3642571                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              13586                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6793                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    272328046.518475                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   432907003.390448                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6793    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value       169000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6793                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   116817756000                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      3933484352                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6793                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    163848                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   56217     40.17%     40.17% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.26% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1975      1.41%     41.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    433      0.31%     41.98% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  81195     58.02%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              139951                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    55705     49.07%     49.07% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.12%     49.19% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1975      1.74%     50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     433      0.38%     51.31% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   55272     48.69%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               113516                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1903162232500     96.77%     96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               93267000      0.00%     96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              789745000      0.04%     96.81% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              321096500      0.02%     96.83% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            62375109000      3.17%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1966741450000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.990892                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.680732                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811112                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  525      0.35%      0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.36% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.36% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3063      2.07%      2.43% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.46% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.46% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               132999     89.79%     92.25% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6513      4.40%     96.65% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.65% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.65% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.66% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.66% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4412      2.98%     99.64% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 394      0.27%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                148123                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6987                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1370                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1369                      
-system.cpu0.kern.mode_good::user                 1370                      
-system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.195935                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.327749                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1962822047500     99.80%     99.80% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3919400500      0.20%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3064                       # number of times the context was actually changed
-system.cpu0.committedInsts                   47693300                       # Number of instructions committed
-system.cpu0.committedOps                     47693300                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44245928                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                210005                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1191022                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5607802                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44245928                       # number of integer instructions
-system.cpu0.num_fp_insts                       210005                       # number of float instructions
-system.cpu0.num_int_register_reads           60860766                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          32957591                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              102620                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             104398                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12600240                       # number of memory refs
-system.cpu0.num_load_insts                    7507148                       # Number of load instructions
-system.cpu0.num_store_insts                   5093092                       # Number of store instructions
-system.cpu0.num_idle_cycles              3699848839.998118                       # Number of idle cycles
-system.cpu0.num_busy_cycles              233635512.001881                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.059397                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.940603                       # Percentage of idle cycles
-system.cpu0.Branches                          7183589                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2715591      5.69%      5.69% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 31389831     65.80%     71.50% # Class of executed instruction
-system.cpu0.op_class::IntMult                   52060      0.11%     71.61% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  26674      0.06%     71.66% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.66% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.66% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.66% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc                  0      0.00%     71.66% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1883      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::FloatMisc                     0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.67% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7588720     15.91%     87.57% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5010315     10.50%     98.08% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead              92556      0.19%     98.27% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite             88892      0.19%     98.46% # Class of executed instruction
-system.cpu0.op_class::IprAccess                735794      1.54%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  47702316                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1183155                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.237754                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11370167                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1183667                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.605883                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        121324500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.237754                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986792                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986792                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51474763                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51474763                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6401125                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6401125                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4669512                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4669512                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138994                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       138994                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       146310                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       146310                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11070637                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11070637                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11070637                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11070637                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       938392                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       938392                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       255335                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       255335                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13590                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13590                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5728                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5728                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1193727                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1193727                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1193727                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1193727                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  31214419000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  31214419000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12662507500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  12662507500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150368000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    150368000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     31952500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     31952500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  43876926500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  43876926500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  43876926500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  43876926500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7339517                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7339517                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4924847                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4924847                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       152584                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       152584                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       152038                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       152038                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12264364                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12264364                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12264364                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12264364                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127855                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127855                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051846                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051846                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089066                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089066                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037675                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037675                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097333                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.097333                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097333                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.097333                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5578.299581                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5578.299581                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       681263                       # number of writebacks
-system.cpu0.dcache.writebacks::total           681263                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       938392                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       938392                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       255335                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       255335                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13590                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13590                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5728                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5728                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1193727                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1193727                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1193727                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1193727                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7073                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7073                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10752                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10752                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17825                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17825                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30276027000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30276027000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12407172500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12407172500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    136778000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136778000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     26224500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     26224500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  42683199500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  42683199500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  42683199500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  42683199500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1572134500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1572134500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1572134500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1572134500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127855                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127855                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051846                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051846                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089066                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089066                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037675                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037675                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097333                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.097333                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097333                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.097333                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4578.299581                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4578.299581                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           692168                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          507.922544                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47009511                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           692680                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.866130                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      44813247500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   507.922544                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992036                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992036                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          435                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48395123                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48395123                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47009511                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47009511                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47009511                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47009511                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47009511                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47009511                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       692806                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       692806                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       692806                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        692806                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       692806                       # number of overall misses
-system.cpu0.icache.overall_misses::total       692806                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10342349000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10342349000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10342349000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10342349000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10342349000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10342349000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     47702317                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47702317                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     47702317                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47702317                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     47702317                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47702317                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014524                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014524                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014524                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014524                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014524                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014524                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14928.203566                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14928.203566                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       692168                       # number of writebacks
-system.cpu0.icache.writebacks::total           692168                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       692806                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       692806                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       692806                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       692806                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       692806                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       692806                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9649543000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9649543000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9649543000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9649543000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9649543000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9649543000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014524                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014524                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014524                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014524                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014524                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014524                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566                       # average overall mshr miss latency
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2442461                       # DTB read hits
-system.cpu1.dtb.read_misses                      2621                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  205338                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1749247                       # DTB write hits
-system.cpu1.dtb.write_misses                      236                       # DTB write misses
-system.cpu1.dtb.write_acv                          24                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  89740                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4191708                       # DTB hits
-system.cpu1.dtb.data_misses                      2857                       # DTB misses
-system.cpu1.dtb.data_acv                           24                       # DTB access violations
-system.cpu1.dtb.data_accesses                  295078                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1826964                       # ITB hits
-system.cpu1.itb.fetch_misses                     1064                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1828028                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5609                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2805                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    692201198.395722                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   417085998.942743                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2805    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value        61500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value    974672500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2805                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    25117814500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      3931646343                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2805                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     79704                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   27198     38.42%     38.42% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      2.78%     41.20% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    525      0.74%     41.94% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  41099     58.06%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               70791                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    26333     48.20%     48.20% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      3.60%     51.80% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     525      0.96%     52.76% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   25808     47.24%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                54635                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1909855455500     97.15%     97.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              731138500      0.04%     97.19% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              371933000      0.02%     97.21% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            54864614500      2.79%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1965823141500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.968196                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.627947                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.771779                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  433      0.59%      0.59% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2016      2.75%      3.35% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.35% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.36% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                64571     88.14%     91.50% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2334      3.19%     94.68% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.68% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     94.69% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.69% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3725      5.08%     99.78% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 73263                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1964                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2923                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                816                      
-system.cpu1.kern.mode_good::user                  367                      
-system.cpu1.kern.mode_good::idle                  449                      
-system.cpu1.kern.mode_switch_good::kernel     0.415479                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.153609                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.310620                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       18379231500      0.94%      0.94% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1492112000      0.08%      1.01% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1945079443000     98.99%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2017                       # number of times the context was actually changed
-system.cpu1.committedInsts                   13268542                       # Number of instructions committed
-system.cpu1.committedOps                     13268542                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             12224320                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                175144                       # Number of float alu accesses
-system.cpu1.num_func_calls                     423403                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1315333                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    12224320                       # number of integer instructions
-system.cpu1.num_fp_insts                       175144                       # number of float instructions
-system.cpu1.num_int_register_reads           16795598                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8988647                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               90944                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              92918                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4214775                       # number of memory refs
-system.cpu1.num_load_insts                    2456291                       # Number of load instructions
-system.cpu1.num_store_insts                   1758484                       # Number of store instructions
-system.cpu1.num_idle_cycles              3881434187.727123                       # Number of idle cycles
-system.cpu1.num_busy_cycles              50212155.272877                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012771                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987229                       # Percentage of idle cycles
-system.cpu1.Branches                          1898911                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               719210      5.42%      5.42% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  7860972     59.23%     64.65% # Class of executed instruction
-system.cpu1.op_class::IntMult                   22603      0.17%     64.82% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.82% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  13252      0.10%     64.92% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.92% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.92% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.92% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc                  0      0.00%     64.92% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1759      0.01%     64.93% # Class of executed instruction
-system.cpu1.op_class::FloatMisc                     0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.93% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2447819     18.44%     83.38% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1681290     12.67%     96.05% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead              81935      0.62%     96.67% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite             78198      0.59%     97.25% # Class of executed instruction
-system.cpu1.op_class::IprAccess                364385      2.75%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  13271423                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           162127                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          484.320008                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4015090                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           162456                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.714938                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      72636345500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   484.320008                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.945938                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.945938                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16996743                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16996743                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2273788                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2273788                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1634135                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1634135                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        51915                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        51915                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        52085                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        52085                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3907923                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3907923                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3907923                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3907923                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       118690                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       118690                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        58791                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        58791                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9152                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9152                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6117                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         6117                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       177481                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        177481                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       177481                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       177481                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1467443500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1467443500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1300528500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1300528500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     84062000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     84062000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     34151000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     34151000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2767972000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2767972000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2767972000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2767972000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2392478                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2392478                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1692926                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1692926                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        61067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        61067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        58202                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        58202                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4085404                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4085404                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4085404                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4085404                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049610                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049610                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034727                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.034727                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.149868                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.149868                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105099                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105099                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043443                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.043443                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043443                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043443                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9185.096154                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9185.096154                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5582.965506                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5582.965506                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       111642                       # number of writebacks
-system.cpu1.dcache.writebacks::total           111642                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118690                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       118690                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        58791                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        58791                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9152                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9152                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6117                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         6117                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       177481                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       177481                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       177481                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       177481                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          125                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total          125                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3371                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3371                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3496                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3496                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1348753500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1348753500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1241737500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1241737500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74910000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74910000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     28034000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     28034000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2590491000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2590491000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2590491000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2590491000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     26291000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     26291000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     26291000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total     26291000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049610                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049610                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034727                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034727                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.149868                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.149868                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105099                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105099                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043443                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043443                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043443                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043443                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8185.096154                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8185.096154                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4582.965506                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4582.965506                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data       210328                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total       210328                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data  7520.308924                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total  7520.308924                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           326560                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          445.783409                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12944312                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           327071                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.576459                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1960887860500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   445.783409                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.870671                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.870671                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          434                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13598534                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13598534                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12944312                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12944312                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12944312                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12944312                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12944312                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12944312                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       327111                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       327111                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       327111                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        327111                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       327111                       # number of overall misses
-system.cpu1.icache.overall_misses::total       327111                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4448984500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4448984500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4448984500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4448984500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4448984500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4448984500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13271423                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13271423                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13271423                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13271423                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13271423                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13271423                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024648                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024648                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024648                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024648                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024648                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024648                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13600.840388                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13600.840388                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       326560                       # number of writebacks
-system.cpu1.icache.writebacks::total           326560                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       327111                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       327111                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       327111                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       327111                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       327111                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       327111                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4121873500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4121873500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4121873500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4121873500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4121873500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4121873500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024648                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024648                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024648                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024648                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024648                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024648                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388                       # average overall mshr miss latency
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55675                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55675                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14036                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42642                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83460                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  126102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56144                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        82394                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2744042                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             15108500                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               758500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15840500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2459000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6051000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216236013                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28519000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41956000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41698                       # number of replacements
-system.iocache.tags.tagsinuse                0.568425                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1760410358000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.568425                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035527                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035527                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375570                       # Number of tag accesses
-system.iocache.tags.data_accesses              375570                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
-system.iocache.overall_misses::total            41730                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22412883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22412883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4955951130                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4955951130                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4978364013                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4978364013                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4978364013                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4978364013                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125915.073034                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119299.401222                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119299.401222                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs          1665                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   10                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs   166.500000                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13512883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13512883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2875898127                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2875898127                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2889411010                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2889411010                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2889411010                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2889411010                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 69240.618500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 69240.618500                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   342924                       # number of replacements
-system.l2c.tags.tagsinuse                65389.954347                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3989934                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   408445                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.768596                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7750508000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     285.827021                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4794.067634                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    59305.224879                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      165.844219                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      838.990595                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.004361                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073152                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.904926                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002531                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.012802                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997772                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65521                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          697                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1597                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6182                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        57022                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999771                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 35598107                       # Number of tag accesses
-system.l2c.tags.data_accesses                35598107                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       792905                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          792905                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       747283                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          747283                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            3151                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            2387                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                5538                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           946                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           957                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              1903                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           128511                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            43286                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               171797                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        680335                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        326126                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1006461                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       663262                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       108452                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           771714                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              680335                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              791773                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              326126                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              151738                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1949972                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             680335                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             791773                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             326126                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             151738                       # number of overall hits
-system.l2c.overall_hits::total                1949972                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data             5                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data             1                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 6                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         116816                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           6419                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             123235                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        12450                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst          984                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           13434                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       271517                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          339                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         271856                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             12450                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            388333                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               984                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              6758                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                408525                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            12450                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           388333                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              984                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             6758                       # number of overall misses
-system.l2c.overall_misses::total               408525                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data       300000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data        28500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       328500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  10623244500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    659466000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11282710500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1281529500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    100368000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1381897500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  21945590000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data     41766500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  21987356500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1281529500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  32568834500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    100368000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    701232500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     34651964500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1281529500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  32568834500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    100368000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    701232500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    34651964500                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       792905                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       792905                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       747283                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       747283                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3156                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2388                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5544                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          946                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          957                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1903                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       245327                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        49705                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295032                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       692785                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       327110                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1019895                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       934779                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       108791                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1043570                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          692785                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1180106                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          327110                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          158496                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2358497                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         692785                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1180106                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         327110                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         158496                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2358497                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.001584                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.000419                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.001082                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.476164                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.129142                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.417700                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.017971                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.003008                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013172                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.290461                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.003116                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.260506                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.017971                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.329066                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.003008                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.042638                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173214                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.017971                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.329066                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.003008                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.042638                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173214                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data        60000                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        28500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total        54750                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90939.978256                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102736.563328                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 91554.432588                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 102934.096386                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst       102000                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 102865.676641                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80825.841476                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123205.014749                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 80878.687614                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 102934.096386                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 83868.315338                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst       102000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 103763.317550                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 84822.139404                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 102934.096386                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 83868.315338                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst       102000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 103763.317550                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 84822.139404                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               79955                       # number of writebacks
-system.l2c.writebacks::total                    79955                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data            5                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data            1                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       116816                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         6419                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        123235                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        12450                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          973                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        13423                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       271517                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          339                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       271856                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        12450                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       388333                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          973                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         6758                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           408514                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        12450                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       388333                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          973                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         6758                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          408514                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7073                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data          125                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         7198                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10752                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3371                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        14123                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17825                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3496                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        21321                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       250000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        18500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       268500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9455084500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    595276000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  10050360500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1157029500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     89768000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1246797500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19230420000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     38376500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  19268796500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1157029500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  28685504500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     89768000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    633652500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  30565954500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1157029500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  28685504500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     89768000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    633652500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  30565954500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1483681000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     24728000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1508409000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1483681000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data     24728000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1508409000                       # number of overall MSHR uncacheable cycles
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.001584                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.000419                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.001082                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.476164                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.129142                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.417700                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.017971                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002975                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013161                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.290461                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.003116                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260506                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017971                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.329066                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002975                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.042638                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173209                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017971                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.329066                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002975                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.042638                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173209                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        50000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        18500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        44750                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 74822.293728                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 74822.293728                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data       197824                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  7073.226545                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        856478                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       407046                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          512                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7198                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292655                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14123                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14123                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       121475                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262336                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            11690                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           9942                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            123955                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           123087                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        285457                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp          148                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42642                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1181082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1223724                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83443                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83443                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1307167                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82394                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31235712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31318106                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33976346                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            22923                       # Total snoops (count)
-system.membus.snoopTraffic                      27264                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            493917                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001373                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.037025                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  493239     99.86%     99.86% # Request fanout histogram
-system.membus.snoop_fanout::1                     678      0.14%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              493917                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40493500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1322925099                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2182236750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy            1074598                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      4789722                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2388089                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       374620                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            991                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          930                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops           61                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7198                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2107102                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14123                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14123                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       872860                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1018728                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          815346                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           17080                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11845                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          28925                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           297046                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297046                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1019917                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1079990                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq          246                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp            4                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2077759                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3616208                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       980781                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       523727                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7198475                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     88636992                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119193988                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     41834880                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     17315286                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              266981146                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          403271                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   7578112                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          2790369                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.143087                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.350419                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2391353     85.70%     85.70% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 398767     14.29%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    248      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2790369                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4224217497                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           304383                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1039374668                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1817986111                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         491891046                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         276353266                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
deleted file mode 100644
index fff26b3..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
deleted file mode 100644
index 7a4d88e..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ /dev/null
@@ -1,1346 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=system.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727:0:0:0:0
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
deleted file mode 100755
index a8a3639..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ /dev/null
@@ -1,6 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
deleted file mode 100755
index 1d59c0e..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:45
-gem5 executing on e108600-lin, pid 28068
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1926421414000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
deleted file mode 100644
index 0bead1a..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ /dev/null
@@ -1,1226 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.926422                       # Number of seconds simulated
-sim_ticks                                1926421638000                       # Number of ticks simulated
-final_tick                               1926421638000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1739419                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1739418                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            59628989604                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 334072                       # Number of bytes of host memory used
-host_seconds                                    32.31                       # Real time elapsed on the host
-sim_insts                                    56195014                       # Number of instructions simulated
-sim_ops                                      56195014                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            844672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24856896                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25702528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       844672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          844672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7408960                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7408960                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13198                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388389                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                401602                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115765                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115765                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               438467                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12903144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               498                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13342109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          438467                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             438467                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3845970                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3845970                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3845970                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              438467                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12903144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              498                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17188079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        401602                       # Number of read requests accepted
-system.physmem.writeReqs                       115765                       # Number of write requests accepted
-system.physmem.readBursts                      401602                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115765                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25695552                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7408000                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25702528                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7408960                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25229                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25631                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25563                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25503                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24978                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24964                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24209                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24494                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25180                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24757                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25269                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24873                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24512                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25367                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25615                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25349                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7626                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7640                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7866                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7539                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7128                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6324                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6321                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7317                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6511                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7117                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6900                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7101                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7827                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7864                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7687                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          65                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1926409764500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  401602                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115765                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    401479                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5581                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      159                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63476                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      521.512887                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     315.060266                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.295929                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14957     23.56%     23.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11430     18.01%     41.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4320      6.81%     48.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3081      4.85%     53.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3222      5.08%     58.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1508      2.38%     60.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1584      2.50%     63.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          999      1.57%     64.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22375     35.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63476                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5049                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        79.519311                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2969.676150                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5046     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5049                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5049                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.925332                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.953728                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.991500                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4538     89.88%     89.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              34      0.67%     90.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             165      3.27%     93.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               7      0.14%     93.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               1      0.02%     93.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              14      0.28%     94.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               8      0.16%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               5      0.10%     94.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              34      0.67%     95.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               2      0.04%     95.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            141      2.79%     98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            16      0.32%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            13      0.26%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             3      0.06%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             6      0.12%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             6      0.12%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             3      0.06%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.04%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            12      0.24%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.08%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            13      0.26%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            10      0.20%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.02%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             6      0.12%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5049                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6110922250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13638916000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2007465000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15220.50                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33970.50                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.34                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.85                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.93                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     360225                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93542                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.72                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3723487.90                       # Average gap between requests
-system.physmem.pageHitRate                      87.73                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  220840200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  117379350                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1432076940                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                299763720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           5519467200.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5038088640                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy              365587680                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy       13029981120                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy        6359365440                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy       449603503800                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy             481990544460                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              250.199922                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime           1914259413500                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE      611958500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2347892000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF   1869275787500                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN  16560859500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9050522500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN  28574618000                       # Time in different power states
-system.physmem_1.actEnergy                  232378440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  123512070                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1434583080                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                304451280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           5706932400.000001                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5156813940                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy              361085280                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy       13650484260                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy        6593796000                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy       449082763260                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy             482651694330                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              250.543123                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime           1914156494000                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE      598122250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2427510000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF   1867055047500                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN  17171481750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9234080250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN  29935396250                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9066536                       # DTB read hits
-system.cpu.dtb.read_misses                      10331                       # DTB read misses
-system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728865                       # DTB read accesses
-system.cpu.dtb.write_hits                     6357492                       # DTB write hits
-system.cpu.dtb.write_misses                      1143                       # DTB write misses
-system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
-system.cpu.dtb.data_hits                     15424028                       # DTB hits
-system.cpu.dtb.data_misses                      11474                       # DTB misses
-system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020797                       # DTB accesses
-system.cpu.itb.fetch_hits                     4975201                       # ITB hits
-system.cpu.itb.fetch_misses                      5010                       # ITB misses
-system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4980211                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12758                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6379                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     281128919.971939                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439406494.656653                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6378     99.98%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6379                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    133100257499                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       3852843276                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     212049                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74911     40.89%     40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1934      1.06%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106246     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183222                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73544     49.31%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1934      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73544     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149153                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1859428733000     96.52%     96.52% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                94503000      0.00%     96.53% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               772464500      0.04%     96.57% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             66125203500      3.43%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1926420904000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692205                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814056                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.16%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175997     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6834      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5159      2.67%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192947                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5906                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.323061                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.391786                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        47043334000      2.44%      2.44% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5370278500      0.28%      2.72% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1874007289500     97.28%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.cpu.committedInsts                    56195014                       # Number of instructions committed
-system.cpu.committedOps                      56195014                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52066552                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483758                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6469897                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52066552                       # number of integer instructions
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            71340789                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38530081                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15476659                       # number of memory refs
-system.cpu.num_load_insts                     9103400                       # Number of load instructions
-system.cpu.num_store_insts                    6373259                       # Number of store instructions
-system.cpu.num_idle_cycles               3586642761.000138                       # Number of idle cycles
-system.cpu.num_busy_cycles               266200514.999862                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.069092                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.930908                       # Percentage of idle cycles
-system.cpu.Branches                           8424278                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3201027      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36239709     64.48%     70.17% # Class of executed instruction
-system.cpu.op_class::IntMult                    61024      0.11%     70.28% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     70.28% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   38087      0.07%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv                    3636      0.01%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::MemRead                  9185894     16.34%     86.70% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6241230     11.10%     97.80% # Class of executed instruction
-system.cpu.op_class::FloatMemRead              144629      0.26%     98.06% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite             138108      0.25%     98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess                 953511      1.70%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56206855                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1390804                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.976541                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14051759                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1391316                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.099617                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         121311500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.976541                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999954                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999954                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63163621                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63163621                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7815914                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815914                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5853567                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5853567                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183003                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183003                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199258                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199258                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13669481                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13669481                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13669481                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13669481                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069734                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069734                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304322                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304322                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17278                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17278                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374056                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374056                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374056                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374056                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33050329500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33050329500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13442227500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13442227500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232507000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    232507000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  46492557000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  46492557000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  46492557000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  46492557000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8885648                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8885648                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157889                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157889                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200281                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200281                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199258                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199258                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15043537                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15043537                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15043537                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15043537                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120389                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120389                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049420                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049420                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086269                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086269                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091339                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091339                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091339                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091339                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33835.998678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33835.998678                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       835203                       # number of writebacks
-system.cpu.dcache.writebacks::total            835203                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069734                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069734                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304322                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304322                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17278                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17278                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374056                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374056                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374056                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374056                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9652                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9652                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16582                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16582                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  31980595500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  31980595500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13137905500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13137905500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215229000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215229000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45118501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45118501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45118501000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45118501000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1533908500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1533908500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1533908500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1533908500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120389                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120389                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049420                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049420                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086269                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086269                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091339                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091339                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091339                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091339                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements            928685                       # number of replacements
-system.cpu.icache.tags.tagsinuse           507.830405                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55277500                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            929196                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.489602                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       44439092500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   507.830405                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.991856                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.991856                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57136212                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57136212                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     55277500                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55277500                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55277500                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55277500                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55277500                       # number of overall hits
-system.cpu.icache.overall_hits::total        55277500                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929356                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929356                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929356                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929356                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929356                       # number of overall misses
-system.cpu.icache.overall_misses::total        929356                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13310087000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13310087000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13310087000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13310087000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13310087000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13310087000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56206856                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56206856                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56206856                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56206856                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56206856                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56206856                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016535                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016535                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016535                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016535                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016535                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016535                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14321.838994                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14321.838994                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks       928685                       # number of writebacks
-system.cpu.icache.writebacks::total            928685                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929356                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929356                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929356                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929356                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929356                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929356                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12380731000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12380731000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12380731000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12380731000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12380731000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12380731000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016535                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016535                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016535                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           336397                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65387.710870                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4236311                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401919                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.540211                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       7724199000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   234.658565                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4730.574877                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.003581                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072183                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.921974                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997737                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          518                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          384                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4685                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59935                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         37511410                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        37511410                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       835203                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       835203                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       928452                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       928452                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187488                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187488                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       916138                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       916138                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       815038                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       815038                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       916138                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002526                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918664                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       916138                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002526                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918664                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116817                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116817                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13198                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        13198                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       271974                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       271974                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13198                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388791                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        401989                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13198                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388791                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       401989                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       246500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       246500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10708900500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10708900500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1353922000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1353922000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  21993208500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  21993208500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1353922000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  32702109000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  34056031000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1353922000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  32702109000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  34056031000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       835203                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       835203                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       928452                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       928452                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304305                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304305                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       929336                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       929336                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1087012                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1087012                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       929336                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1391317                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320653                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       929336                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1391317                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320653                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.294118                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.294118                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383881                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383881                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014202                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014202                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250203                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250203                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014202                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279441                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173222                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014202                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279441                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173222                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        49300                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        49300                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        74253                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74253                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116817                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116817                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        13198                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        13198                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       271974                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       271974                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13198                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388791                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       401989                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        13198                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388791                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       401989                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9652                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9652                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16582                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16582                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       196500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       196500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9540730500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9540730500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1221942000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1221942000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19273468500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19273468500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1221942000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28814199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  30036141000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1221942000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28814199000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30036141000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447252500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447252500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447252500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447252500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.294118                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.294118                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383881                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383881                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014202                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250203                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250203                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279441                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173222                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014202                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279441                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        39300                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        39300                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4640179                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319543                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1996                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          884                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          884                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2023455                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9652                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9652                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       909456                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       928685                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       817745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304305                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304305                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       929356                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1087173                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq          219                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp            1                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2787377                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4206794                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6994171                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118913344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142551908                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          261465252                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      336955                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               4763520                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2674049                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001078                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.032812                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2671167     99.89%     99.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2882      0.11%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2674049                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4097094500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       293883                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1394034000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2098740000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51204                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51204                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5160                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116614                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2706188                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5344000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               757500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15813000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             1891500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6041500                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216206774                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23512000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.342515                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1760392723000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.342515                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.083907                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.083907                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21848883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21848883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4937049891                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4937049891                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4958898774                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4958898774                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4958898774                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4958898774                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126294.121387                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118847.184518                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118847.184518                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           700                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          175                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13198883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13198883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2857005811                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2857005811                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2870204694                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2870204694                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2870204694                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2870204694                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68788.608604                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68788.608604                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests        821141                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       378172                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          503                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292275                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9652                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9652                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115765                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261592                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              136                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116686                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116686                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        285345                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp          124                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139253                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172417                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1255842                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30453760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30498340                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33156068                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              555                       # Total snoops (count)
-system.membus.snoopTraffic                      27456                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            460301                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001419                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.037638                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  459648     99.86%     99.86% # Request fanout histogram
-system.membus.snoop_fanout::1                     653      0.14%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              460301                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30123500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1287046834                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2142988500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy            1022522                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
deleted file mode 100644
index d82c053..0000000
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
deleted file mode 100644
index 0e34b27..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ /dev/null
@@ -1,2188 +0,0 @@
-[drivesys]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu disk0 disk2 dvfs_handler intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=250
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=drivesys.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=drivesys.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/configs/boot/netperf-server.rcS
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=drivesys.membus.slave[0]
-
-[drivesys.bridge]
-type=Bridge
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-master=drivesys.iobus.slave[0]
-slave=drivesys.membus.master[0]
-
-[drivesys.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=drivesys.voltage_domain
-
-[drivesys.cpu]
-type=AtomicSimpleCPU
-children=clk_domain dtb interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=drivesys.cpu.clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=drivesys.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=drivesys.cpu.interrupts
-isa=drivesys.cpu.isa
-itb=drivesys.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=drivesys
-tracer=drivesys.cpu.tracer
-width=1
-workload=
-dcache_port=drivesys.membus.slave[2]
-icache_port=drivesys.membus.slave[1]
-
-[drivesys.cpu.clk_domain]
-type=SrcClockDomain
-clock=250
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=drivesys.voltage_domain
-
-[drivesys.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[drivesys.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[drivesys.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=drivesys
-
-[drivesys.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[drivesys.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[drivesys.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=drivesys.disk0.image
-
-[drivesys.disk0.image]
-type=CowDiskImage
-children=child
-child=drivesys.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[drivesys.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[drivesys.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=drivesys.disk2.image
-
-[drivesys.disk2.image]
-type=CowDiskImage
-children=child
-child=drivesys.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[drivesys.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[drivesys.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=drivesys.clk_domain
-transition_latency=100000000
-
-[drivesys.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=drivesys
-
-[drivesys.iobridge]
-type=Bridge
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=0:134217727
-req_size=16
-resp_size=16
-master=drivesys.membus.slave[3]
-slave=drivesys.iobus.master[27]
-
-[drivesys.iobus]
-type=NoncoherentXBar
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.iobridge.slave
-slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
-
-[drivesys.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=drivesys
-use_default_range=false
-width=16
-default=drivesys.membus.badaddr_responder.pio
-master=drivesys.bridge.slave drivesys.physmem.port
-slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
-
-[drivesys.membus.badaddr_responder]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.membus.default
-
-[drivesys.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=drivesys.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=drivesys.membus.master[1]
-
-[drivesys.simple_disk]
-type=SimpleDisk
-children=disk
-disk=drivesys.simple_disk.disk
-eventq_index=0
-system=drivesys
-
-[drivesys.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[drivesys.terminal]
-type=Terminal
-eventq_index=0
-intr_control=drivesys.intrctrl
-number=0
-output=true
-port=3456
-
-[drivesys.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=drivesys.intrctrl
-system=drivesys
-
-[drivesys.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=drivesys.clk_domain
-cpu=drivesys.cpu
-default_p_state=UNDEFINED
-disk=drivesys.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=drivesys.tsunami
-power_model=Null
-system=drivesys
-terminal=drivesys.terminal
-pio=drivesys.iobus.master[24]
-
-[drivesys.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=drivesys
-tsunami=drivesys.tsunami
-pio=drivesys.iobus.master[0]
-
-[drivesys.tsunami.ethernet]
-type=NSGigE
-children=clk_domain
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=drivesys.tsunami.ethernet.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=drivesys.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=drivesys
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=drivesys.iobus.slave[2]
-interface=etherlink.int1
-pio=drivesys.iobus.master[26]
-
-[drivesys.tsunami.ethernet.clk_domain]
-type=SrcClockDomain
-clock=2000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=drivesys.voltage_domain
-
-[drivesys.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[8]
-
-[drivesys.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[19]
-
-[drivesys.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[20]
-
-[drivesys.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[9]
-
-[drivesys.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[11]
-
-[drivesys.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[12]
-
-[drivesys.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[13]
-
-[drivesys.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[14]
-
-[drivesys.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[15]
-
-[drivesys.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[16]
-
-[drivesys.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[17]
-
-[drivesys.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[18]
-
-[drivesys.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[10]
-
-[drivesys.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[7]
-
-[drivesys.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[2]
-
-[drivesys.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[3]
-
-[drivesys.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[4]
-
-[drivesys.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[5]
-
-[drivesys.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=drivesys
-update_data=false
-warn_access=
-pio=drivesys.iobus.master[6]
-
-[drivesys.tsunami.fb]
-type=BadDevice
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=drivesys
-pio=drivesys.iobus.master[21]
-
-[drivesys.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=drivesys.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=drivesys.disk0 drivesys.disk2
-eventq_index=0
-host=drivesys.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=drivesys
-dma=drivesys.iobus.slave[1]
-pio=drivesys.iobus.master[25]
-
-[drivesys.tsunami.io]
-type=TsunamiIO
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=drivesys
-time=Thu Jan  1 00:00:00 2009
-tsunami=drivesys.tsunami
-year_is_bcd=false
-pio=drivesys.iobus.master[22]
-
-[drivesys.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=drivesys.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=drivesys.tsunami
-power_model=Null
-system=drivesys
-tsunami=drivesys.tsunami
-pio=drivesys.iobus.master[1]
-
-[drivesys.tsunami.uart]
-type=Uart8250
-clk_domain=drivesys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=drivesys.tsunami
-power_model=Null
-system=drivesys
-terminal=drivesys.terminal
-pio=drivesys.iobus.master[23]
-
-[drivesys.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[etherdump]
-type=EtherDump
-eventq_index=0
-file=ethertrace
-maxlen=96
-
-[etherlink]
-type=EtherLink
-delay=0
-delay_var=0
-dump=etherdump
-eventq_index=0
-speed=8000.000000
-int0=testsys.tsunami.ethernet.interface
-int1=drivesys.tsunami.ethernet.interface
-
-[root]
-type=Root
-children=drivesys etherdump etherlink testsys
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[testsys]
-type=LinuxAlphaSystem
-children=bridge clk_domain cpu disk0 disk2 dvfs_handler intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain
-boot_cpu_frequency=500
-boot_osflags=root=/dev/hda1 console=ttyS0
-cache_line_size=64
-clk_domain=testsys.clk_domain
-console=/arm/projectscratch/randd/systems/dist/binaries/console
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=testsys.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/configs/boot/netperf-stream-client.rcS
-symbolfile=
-system_rev=1024
-system_type=34
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=testsys.membus.slave[0]
-
-[testsys.bridge]
-type=Bridge
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=8796093022208:18446744073709551615
-req_size=16
-resp_size=16
-master=testsys.iobus.slave[0]
-slave=testsys.membus.master[0]
-
-[testsys.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=testsys.voltage_domain
-
-[testsys.cpu]
-type=AtomicSimpleCPU
-children=clk_domain dtb interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=testsys.cpu.clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=testsys.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=testsys.cpu.interrupts
-isa=testsys.cpu.isa
-itb=testsys.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=testsys
-tracer=testsys.cpu.tracer
-width=1
-workload=
-dcache_port=testsys.membus.slave[2]
-icache_port=testsys.membus.slave[1]
-
-[testsys.cpu.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=testsys.voltage_domain
-
-[testsys.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[testsys.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[testsys.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=testsys
-
-[testsys.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[testsys.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[testsys.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=testsys.disk0.image
-
-[testsys.disk0.image]
-type=CowDiskImage
-children=child
-child=testsys.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[testsys.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[testsys.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=testsys.disk2.image
-
-[testsys.disk2.image]
-type=CowDiskImage
-children=child
-child=testsys.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[testsys.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[testsys.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=testsys.clk_domain
-transition_latency=100000000
-
-[testsys.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=testsys
-
-[testsys.iobridge]
-type=Bridge
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=0:134217727
-req_size=16
-resp_size=16
-master=testsys.membus.slave[3]
-slave=testsys.iobus.master[27]
-
-[testsys.iobus]
-type=NoncoherentXBar
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.iobridge.slave
-slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
-
-[testsys.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=testsys
-use_default_range=false
-width=16
-default=testsys.membus.badaddr_responder.pio
-master=testsys.bridge.slave testsys.physmem.port
-slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
-
-[testsys.membus.badaddr_responder]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.membus.default
-
-[testsys.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=testsys.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=testsys.membus.master[1]
-
-[testsys.simple_disk]
-type=SimpleDisk
-children=disk
-disk=testsys.simple_disk.disk
-eventq_index=0
-system=testsys
-
-[testsys.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[testsys.terminal]
-type=Terminal
-eventq_index=0
-intr_control=testsys.intrctrl
-number=0
-output=true
-port=3456
-
-[testsys.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=testsys.intrctrl
-system=testsys
-
-[testsys.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=testsys.clk_domain
-cpu=testsys.cpu
-default_p_state=UNDEFINED
-disk=testsys.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=testsys.tsunami
-power_model=Null
-system=testsys
-terminal=testsys.terminal
-pio=testsys.iobus.master[24]
-
-[testsys.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=testsys
-tsunami=testsys.tsunami
-pio=testsys.iobus.master[0]
-
-[testsys.tsunami.ethernet]
-type=NSGigE
-children=clk_domain
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=testsys.tsunami.ethernet.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:02
-host=testsys.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=testsys
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=testsys.iobus.slave[2]
-interface=etherlink.int0
-pio=testsys.iobus.master[26]
-
-[testsys.tsunami.ethernet.clk_domain]
-type=SrcClockDomain
-clock=2000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=testsys.voltage_domain
-
-[testsys.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[8]
-
-[testsys.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[19]
-
-[testsys.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[20]
-
-[testsys.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[9]
-
-[testsys.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[11]
-
-[testsys.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[12]
-
-[testsys.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[13]
-
-[testsys.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[14]
-
-[testsys.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[15]
-
-[testsys.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[16]
-
-[testsys.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[17]
-
-[testsys.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[18]
-
-[testsys.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[10]
-
-[testsys.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[7]
-
-[testsys.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[2]
-
-[testsys.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[3]
-
-[testsys.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[4]
-
-[testsys.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[5]
-
-[testsys.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=testsys
-update_data=false
-warn_access=
-pio=testsys.iobus.master[6]
-
-[testsys.tsunami.fb]
-type=BadDevice
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=testsys
-pio=testsys.iobus.master[21]
-
-[testsys.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=testsys.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=testsys.disk0 testsys.disk2
-eventq_index=0
-host=testsys.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=testsys
-dma=testsys.iobus.slave[1]
-pio=testsys.iobus.master[25]
-
-[testsys.tsunami.io]
-type=TsunamiIO
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=testsys
-time=Thu Jan  1 00:00:00 2009
-tsunami=testsys.tsunami
-year_is_bcd=false
-pio=testsys.iobus.master[22]
-
-[testsys.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=testsys.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=testsys.tsunami
-power_model=Null
-system=testsys
-tsunami=testsys.tsunami
-pio=testsys.iobus.master[1]
-
-[testsys.tsunami.uart]
-type=Uart8250
-clk_domain=testsys.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=testsys.tsunami
-power_model=Null
-system=testsys
-terminal=testsys.terminal
-pio=testsys.iobus.master[23]
-
-[testsys.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
deleted file mode 100644
index d2dce78..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
deleted file mode 100755
index c3ad78f..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Obsolete M5 ivlb instruction encountered.
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
deleted file mode 100755
index 51edd98..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ /dev/null
@@ -1,17 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:23
-gem5 executing on e108600-lin, pid 39549
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
-      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 4321620817500 because checkpoint
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
deleted file mode 100644
index 8392619..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ /dev/null
@@ -1,1323 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.200409                       # Number of seconds simulated
-sim_ticks                                200409271000                       # Number of ticks simulated
-final_tick                               4321213476000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               18920085                       # Simulator instruction rate (inst/s)
-host_op_rate                                 18920078                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7239205973                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 501524                       # Number of bytes of host memory used
-host_seconds                                    27.68                       # Real time elapsed on the host
-sim_insts                                   523780905                       # Number of instructions simulated
-sim_ops                                     523780905                       # Number of ops (including micro ops) simulated
-drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
-drivesys.clk_domain.clock                        1000                       # Clock period in ticks
-drivesys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.physmem.bytes_read::cpu.inst        76205572                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data        26284292                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet     57260550                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total          159750414                       # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst     76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total      76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data     14619632                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::tsunami.ethernet         1064                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total        14620696                       # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst         19051393                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data          3647049                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet      2385839                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total            25084281                       # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data         2024776                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::tsunami.ethernet           37                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total            2024813                       # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst          380249734                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data          131153074                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet    285718069                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total             797120878                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst     380249734                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total        380249734                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data          72948881                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::tsunami.ethernet         5309                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total             72954190                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst         380249734                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data         204101955                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet    285723379                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total            870075068                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.read_hits                    3725273                       # DTB read hits
-drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
-drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
-drivesys.cpu.dtb.read_accesses                 267991                       # DTB read accesses
-drivesys.cpu.dtb.write_hits                   2084079                       # DTB write hits
-drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
-drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
-drivesys.cpu.dtb.write_accesses                133239                       # DTB write accesses
-drivesys.cpu.dtb.data_hits                    5809352                       # DTB hits
-drivesys.cpu.dtb.data_misses                      569                       # DTB misses
-drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
-drivesys.cpu.dtb.data_accesses                 401230                       # DTB accesses
-drivesys.cpu.itb.fetch_hits                   4197628                       # ITB hits
-drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
-drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
-drivesys.cpu.itb.fetch_accesses               4197822                       # ITB accesses
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.numPwrStateTransitions             39752                       # Number of power state transitions
-drivesys.cpu.pwrStateClkGateDist::samples        19877                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::mean   9843365.409770                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::stdev  830979.613808                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::1000-5e+10        19877    100.00%    100.00% # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::min_value        25500                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::max_value      9947500                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::total         19877                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateResidencyTicks::ON    4757933250                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.pwrStateResidencyTicks::CLK_GATED 195656574250                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.numCycles                      801651324                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                  60359     42.42%     42.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                 19727     13.86%     56.28% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                   205      0.14%     56.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                 62011     43.58%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total             142302                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                   60359     42.91%     42.91% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                  19727     14.03%     56.94% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                    205      0.15%     57.09% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                  60360     42.91%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total              140651                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0           197399332500     98.50%     98.50% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21             798910750      0.40%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22               4407500      0.00%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31            2205211250      1.10%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total       200407862000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.973376                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.988398                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.callpal::swpctx                  72      0.06%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::tbi                      5      0.00%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl              102333     83.31%     83.37% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                   354      0.29%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rdusp                    1      0.00%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                  20038     16.31%     99.97% # number of callpals executed
-drivesys.cpu.kern.callpal::callsys                 25      0.02%     99.99% # number of callpals executed
-drivesys.cpu.kern.callpal::imb                      7      0.01%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total               122835                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel             214                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user               140                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle             19896                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel               144                      
-drivesys.cpu.kern.mode_good::user                 140                      
-drivesys.cpu.kern.mode_good::idle                   4                      
-drivesys.cpu.kern.mode_switch_good::kernel     0.672897                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     0.000201                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     0.014222                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel         78134250      2.63%      2.63% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
-drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
-drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
-drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
-drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
-drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
-drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             782619252.927065                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             19032071.072935                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.023741                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.976259                       # Percentage of idle cycles
-drivesys.cpu.Branches                         2793313                       # Number of branches fetched
-drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
-drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
-drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatMultAcc                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatMisc                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::MemRead                4025389     21.13%     85.08% # Class of executed instruction
-drivesys.cpu.op_class::MemWrite               2084412     10.94%     96.02% # Class of executed instruction
-drivesys.cpu.op_class::FloatMemRead               639      0.00%     96.02% # Class of executed instruction
-drivesys.cpu.op_class::FloatMemWrite              609      0.00%     96.02% # Class of executed instruction
-drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.iobus.trans_dist::ReadReq            2484469                       # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp           2484469                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq             39723                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp            39723                       # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio       197670                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio        78962                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total       276632                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total               5048384                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio       790680                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio       157924                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total       948604                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total               58210218                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoop_filter.tot_requests            0                       # Total number of requests made to the snoop filter.
-drivesys.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-drivesys.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-drivesys.membus.snoop_filter.tot_snoops             0                       # Total number of snoops made to the snoop filter.
-drivesys.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-drivesys.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-drivesys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.membus.trans_dist::ReadReq          25081955                       # Transaction distribution
-drivesys.membus.trans_dist::ReadResp         25182911                       # Transaction distribution
-drivesys.membus.trans_dist::WriteReq          1963575                       # Transaction distribution
-drivesys.membus.trans_dist::WriteResp         1963575                       # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq       100956                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq       100924                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp       100924                       # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port     38102786                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total     38102786                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave       276632                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port     11343650                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total     11620282                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total             54494820                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port     76205572                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total     76205572                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave       948604                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port     40903924                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total     41852528                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total             175319714                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops                              0                       # Total snoops (count)
-drivesys.membus.snoopTraffic                        0                       # Total snoop traffic (bytes)
-drivesys.membus.snoop_fanout::samples        27247410                       # Request fanout histogram
-drivesys.membus.snoop_fanout::mean                  0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev                 0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0              27247410    100.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::1                     0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::total          27247410                       # Request fanout histogram
-drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
-drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
-drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
-drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
-drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
-drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
-drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
-drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
-drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads        2385810                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes     57259440                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.totBandwidth          70176                       # Total Bandwidth (bits/s)
-drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
-drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
-drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txBandwidth           31855                       # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBandwidth           38322                       # Receive Bandwidth (bits/s)
-drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc              8                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle          19726                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle         2385810                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts      2385831                       # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.voltage_domain.voltage                      1                       # Voltage in Volts
-testsys.clk_domain.clock                         1000                       # Clock period in ticks
-testsys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.physmem.bytes_read::cpu.inst         81044080                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data         27825116                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet     57260496                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::total           166129692                       # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst     81044080                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total       81044080                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data      16605404                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::tsunami.ethernet          902                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::total         16606306                       # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst          20261020                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data           3842409                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet      2385836                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total             26489265                       # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data          2258228                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::tsunami.ethernet           31                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total             2258259                       # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst           404392869                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data           138841461                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet    285717800                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total              828952130                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst      404392869                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total         404392869                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data           82857464                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::tsunami.ethernet         4501                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total              82861965                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst          404392869                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data          221698925                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet    285722301                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total             911814095                       # Total bandwidth to/from this memory (bytes/s)
-testsys.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
-testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
-testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.read_hits                     3916768                       # DTB read hits
-testsys.cpu.dtb.read_misses                      3287                       # DTB read misses
-testsys.cpu.dtb.read_acv                           80                       # DTB read access violations
-testsys.cpu.dtb.read_accesses                  225414                       # DTB read accesses
-testsys.cpu.dtb.write_hits                    2316721                       # DTB write hits
-testsys.cpu.dtb.write_misses                      528                       # DTB write misses
-testsys.cpu.dtb.write_acv                          81                       # DTB write access violations
-testsys.cpu.dtb.write_accesses                 109988                       # DTB write accesses
-testsys.cpu.dtb.data_hits                     6233489                       # DTB hits
-testsys.cpu.dtb.data_misses                      3815                       # DTB misses
-testsys.cpu.dtb.data_acv                          161                       # DTB access violations
-testsys.cpu.dtb.data_accesses                  335402                       # DTB accesses
-testsys.cpu.itb.fetch_hits                    4052237                       # ITB hits
-testsys.cpu.itb.fetch_misses                     1497                       # ITB misses
-testsys.cpu.itb.fetch_acv                          69                       # ITB acv
-testsys.cpu.itb.fetch_accesses                4053734                       # ITB accesses
-testsys.cpu.itb.read_hits                           0                       # DTB read hits
-testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.write_hits                          0                       # DTB write hits
-testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.numPwrStateTransitions              39159                       # Number of power state transitions
-testsys.cpu.pwrStateClkGateDist::samples        19580                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::mean    9718476.378958                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::stdev   783559.874332                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::1000-5e+10        19580    100.00%    100.00% # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::min_value       105000                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::max_value      9815000                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::total          19580                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateResidencyTicks::ON    11102310500                       # Cumulative time (in ticks) in various power states
-testsys.cpu.pwrStateResidencyTicks::CLK_GATED 190287767500                       # Cumulative time (in ticks) in various power states
-testsys.cpu.numCycles                       400825859                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                   19580                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                    153669                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                   62779     42.67%     42.67% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                  19625     13.34%     56.01% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                    205      0.14%     56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                  64511     43.85%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total              147120                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                    62773     43.18%     43.18% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                   19625     13.50%     56.67% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                     205      0.14%     56.82% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                   62785     43.18%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total               145388                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0            194347611000     96.98%     96.98% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21             1588986000      0.79%     97.77% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                8815000      0.00%     97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31             4457946500      2.22%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total        200403358500                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                 0.999904                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.973245                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.988227                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpctx                  438      0.34%      0.34% # number of callpals executed
-testsys.cpu.kern.callpal::tbi                      20      0.02%      0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl               106832     83.26%     83.62% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                    359      0.28%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp                     3      0.00%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rdusp                     3      0.00%     83.90% # number of callpals executed
-testsys.cpu.kern.callpal::rti                   20470     15.95%     99.86% # number of callpals executed
-testsys.cpu.kern.callpal::callsys                 140      0.11%     99.97% # number of callpals executed
-testsys.cpu.kern.callpal::imb                      44      0.03%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                128309                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel             1280                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                706                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle              19629                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                711                      
-testsys.cpu.kern.mode_good::user                  706                      
-testsys.cpu.kern.mode_good::idle                    5                      
-testsys.cpu.kern.mode_switch_good::kernel     0.555469                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle      0.000255                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total     0.065788                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel         994253000     59.96%     59.96% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user           533088000     32.15%     92.11% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle           130749000      7.89%    100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
-testsys.cpu.committedInsts                   20257044                       # Number of instructions committed
-testsys.cpu.committedOps                     20257044                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses             18836392                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
-testsys.cpu.num_func_calls                    1221158                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts      1442105                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                    18836392                       # number of integer instructions
-testsys.cpu.num_fp_insts                        17380                       # number of float instructions
-testsys.cpu.num_int_register_reads           24786330                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes          14693469                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                      6262732                       # number of memory refs
-testsys.cpu.num_load_insts                    3943883                       # Number of load instructions
-testsys.cpu.num_store_insts                   2318849                       # Number of store instructions
-testsys.cpu.num_idle_cycles              380582482.461103                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              20243376.538897                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.050504                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.949496                       # Percentage of idle cycles
-testsys.cpu.Branches                          2929782                       # Number of branches fetched
-testsys.cpu.op_class::No_OpClass               712785      3.52%      3.52% # Class of executed instruction
-testsys.cpu.op_class::IntAlu                 12147004     59.95%     63.47% # Class of executed instruction
-testsys.cpu.op_class::IntMult                   21654      0.11%     63.58% # Class of executed instruction
-testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd                   4655      0.02%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp                      1      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatMult                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatMultAcc                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv                    922      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatMisc                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMult                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShift                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::MemRead                 4224290     20.85%     84.45% # Class of executed instruction
-testsys.cpu.op_class::MemWrite                2313781     11.42%     95.87% # Class of executed instruction
-testsys.cpu.op_class::FloatMemRead               6195      0.03%     95.90% # Class of executed instruction
-testsys.cpu.op_class::FloatMemWrite              5607      0.03%     95.93% # Class of executed instruction
-testsys.cpu.op_class::IprAccess                824126      4.07%    100.00% # Class of executed instruction
-testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-testsys.cpu.op_class::total                  20261020                       # Class of executed instruction
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.iobus.trans_dist::ReadReq             2483943                       # Transaction distribution
-testsys.iobus.trans_dist::ReadResp            2483943                       # Transaction distribution
-testsys.iobus.trans_dist::WriteReq              39573                       # Transaction distribution
-testsys.iobus.trans_dist::WriteResp             39573                       # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio       196204                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio          336                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio          428                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio        78330                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total       275298                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave      4771734                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total      4771734                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total                5047032                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio       784816                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio          462                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio          214                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio       156660                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total       942152                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total                58203550                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoop_filter.tot_requests            0                       # Total number of requests made to the snoop filter.
-testsys.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-testsys.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-testsys.membus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-testsys.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-testsys.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-testsys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.membus.trans_dist::ReadReq           26478762                       # Transaction distribution
-testsys.membus.trans_dist::ReadResp          26587372                       # Transaction distribution
-testsys.membus.trans_dist::WriteReq           2189273                       # Transaction distribution
-testsys.membus.trans_dist::WriteResp          2189273                       # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq       108610                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq        108528                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp       108528                       # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port     40522040                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total     40522040                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave       275298                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port     12201274                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total     12476572                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port      4771734                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total      4771734                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total              57770346                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port     81044080                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total     81044080                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave       942152                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port     44430520                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total     45372672                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total              183678150                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops                               0                       # Total snoops (count)
-testsys.membus.snoopTraffic                         0                       # Total snoop traffic (bytes)
-testsys.membus.snoop_fanout::samples         28885173                       # Request fanout histogram
-testsys.membus.snoop_fanout::mean                   0                       # Request fanout histogram
-testsys.membus.snoop_fanout::stdev                  0                       # Request fanout histogram
-testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0               28885173    100.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::max_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::total           28885173                       # Request fanout histogram
-testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
-testsys.tsunami.ethernet.rxBytes                  798                       # Bytes Received
-testsys.tsunami.ethernet.txPackets                  8                       # Number of Packets Transmitted
-testsys.tsunami.ethernet.rxPackets                  5                       # Number of Packets Received
-testsys.tsunami.ethernet.txIpChecksums              2                       # Number of tx IP Checksums done by device
-testsys.tsunami.ethernet.rxIpChecksums              5                       # Number of rx IP Checksums done by device
-testsys.tsunami.ethernet.txTcpChecksums             2                       # Number of tx TCP Checksums done by device
-testsys.tsunami.ethernet.rxTcpChecksums             5                       # Number of rx TCP Checksums done by device
-testsys.tsunami.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-testsys.tsunami.ethernet.rxUdpChecksums             0                       # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads         2385801                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites             13                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes     57259224                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.totBandwidth           70176                       # Total Bandwidth (bits/s)
-testsys.tsunami.ethernet.totPackets                13                       # Total Packets
-testsys.tsunami.ethernet.totBytes                1758                       # Total Bytes
-testsys.tsunami.ethernet.totPPS                    65                       # Total Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txBandwidth            38322                       # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.rxBandwidth            31855                       # Receive Bandwidth (bits/s)
-testsys.tsunami.ethernet.txPPS                     40                       # Packet Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.rxPPS                     25                       # Packet Reception Rate (packets/s)
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc               5                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc                5                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle           19571                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle          2385801                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts      2385819                       # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000407                       # Number of seconds simulated
-sim_ticks                                   407341500                       # Number of ticks simulated
-final_tick                               4321620817500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             9697698249                       # Simulator instruction rate (inst/s)
-host_op_rate                               9695968284                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7538213070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 501524                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-sim_insts                                   523853183                       # Number of instructions simulated
-sim_ops                                     523853183                       # Number of ops (including micro ops) simulated
-drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
-drivesys.clk_domain.clock                        1000                       # Clock period in ticks
-drivesys.physmem.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.physmem.bytes_read::cpu.inst          144608                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data           49952                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet       116400                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total             310960                       # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst       144608                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total        144608                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data        27688                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total           27688                       # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst            36152                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data             6909                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet         4850                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total               47911                       # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data            3812                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total               3812                       # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst          355004339                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data          122629293                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet    285755318                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total             763388950                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst     355004339                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total        355004339                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data          67972451                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total             67972451                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst         355004339                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data         190601743                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet    285755318                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total            831361401                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.bridge.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.read_hits                       7069                       # DTB read hits
-drivesys.cpu.dtb.read_misses                        0                       # DTB read misses
-drivesys.cpu.dtb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.dtb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.dtb.write_hits                      3933                       # DTB write hits
-drivesys.cpu.dtb.write_misses                       0                       # DTB write misses
-drivesys.cpu.dtb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.dtb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.dtb.data_hits                      11002                       # DTB hits
-drivesys.cpu.dtb.data_misses                        0                       # DTB misses
-drivesys.cpu.dtb.data_acv                           0                       # DTB access violations
-drivesys.cpu.dtb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.itb.fetch_hits                      5992                       # ITB hits
-drivesys.cpu.itb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.itb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.itb.fetch_accesses                  5992                       # ITB accesses
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.numPwrStateTransitions                82                       # Number of power state transitions
-drivesys.cpu.pwrStateClkGateDist::samples           42                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::mean   9483660.714286                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::stdev  1743513.957554                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::1000-5e+10           42    100.00%    100.00% # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::min_value       920000                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::max_value      9947500                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateClkGateDist::total            42                       # Distribution of time spent in the clock gated state
-drivesys.cpu.pwrStateResidencyTicks::ON       9027750                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.pwrStateResidencyTicks::CLK_GATED    398313750                       # Cumulative time (in ticks) in various power states
-drivesys.cpu.numCycles                        1626281                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                     41                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                      295                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                    123     41.84%     41.84% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                    40     13.61%     55.44% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                     1      0.34%     55.78% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                   130     44.22%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total                294                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                     123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                     40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                      1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                    123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total                 287                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0              400289000     98.46%     98.46% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21               1620000      0.40%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22                 21500      0.01%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31               4629500      1.14%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total          406560000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.946154                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.976190                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.callpal::swpipl                 212     83.46%     83.46% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                     1      0.39%     83.86% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                     41     16.14%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total                  254                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle                41                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel                 0                      
-drivesys.cpu.kern.mode_good::user                   0                      
-drivesys.cpu.kern.mode_good::idle                   0                      
-drivesys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
-drivesys.cpu.committedInsts                     36152                       # Number of instructions committed
-drivesys.cpu.committedOps                       36152                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses               33516                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                      2388                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts         2347                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                      33516                       # number of integer instructions
-drivesys.cpu.num_fp_insts                           0                       # number of float instructions
-drivesys.cpu.num_int_register_reads             43772                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes            26499                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                       11043                       # number of memory refs
-drivesys.cpu.num_load_insts                      7109                       # Number of load instructions
-drivesys.cpu.num_store_insts                     3934                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             1590238.371734                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             36042.628266                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.022163                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.977837                       # Percentage of idle cycles
-drivesys.cpu.Branches                            5243                       # Number of branches fetched
-drivesys.cpu.op_class::No_OpClass                1262      3.49%      3.49% # Class of executed instruction
-drivesys.cpu.op_class::IntAlu                   21687     59.99%     63.48% # Class of executed instruction
-drivesys.cpu.op_class::IntMult                     44      0.12%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::IntDiv                       0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatAdd                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatMult                    0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatMultAcc                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatDiv                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatMisc                    0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdMult                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdShift                    0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.60% # Class of executed instruction
-drivesys.cpu.op_class::MemRead                   7678     21.24%     84.84% # Class of executed instruction
-drivesys.cpu.op_class::MemWrite                  3936     10.89%     95.73% # Class of executed instruction
-drivesys.cpu.op_class::FloatMemRead                 0      0.00%     95.73% # Class of executed instruction
-drivesys.cpu.op_class::FloatMemWrite                0      0.00%     95.73% # Class of executed instruction
-drivesys.cpu.op_class::IprAccess                 1545      4.27%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::total                    36152                       # Class of executed instruction
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.iobus.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.iobus.trans_dist::ReadReq               5050                       # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp              5050                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq                81                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp               81                       # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave         9700                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total         9700                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total                 10262                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total                 118328                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoop_filter.tot_requests            0                       # Total number of requests made to the snoop filter.
-drivesys.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-drivesys.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-drivesys.membus.snoop_filter.tot_snoops             0                       # Total number of snoops made to the snoop filter.
-drivesys.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-drivesys.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-drivesys.membus.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.membus.trans_dist::ReadReq             47907                       # Transaction distribution
-drivesys.membus.trans_dist::ReadResp            48111                       # Transaction distribution
-drivesys.membus.trans_dist::WriteReq             3689                       # Transaction distribution
-drivesys.membus.trans_dist::WriteResp            3689                       # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq          204                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port        72304                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total        72304                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port        21442                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total        22004                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port         9700                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total         9700                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total               104008                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port       144608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total       144608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total                340576                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops                              0                       # Total snoops (count)
-drivesys.membus.snoopTraffic                        0                       # Total snoop traffic (bytes)
-drivesys.membus.snoop_fanout::samples           52004                       # Request fanout histogram
-drivesys.membus.snoop_fanout::mean                  0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev                 0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0                 52004    100.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::1                     0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::total             52004                       # Request fanout histogram
-drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ethernet.descDMAReads           4850                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes       116400                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc              0                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalRxDesc               0                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle             40                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle            4850                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts         4850                       # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.voltage_domain.voltage                      1                       # Voltage in Volts
-testsys.clk_domain.clock                         1000                       # Clock period in ticks
-testsys.physmem.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data            49936                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet       116376                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::total              310816                       # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst       144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total         144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data         27704                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::total            27704                       # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst             36126                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data              6905                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet         4849                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total                47880                       # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data             3814                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total                3814                       # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst           354749025                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data           122590014                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet    285696400                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total              763035438                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst      354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total         354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data           68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total              68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst          354749025                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data          190601743                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet    285696400                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total             831047168                       # Total bandwidth to/from this memory (bytes/s)
-testsys.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.bridge.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
-testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
-testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.read_hits                        7065                       # DTB read hits
-testsys.cpu.dtb.read_misses                         0                       # DTB read misses
-testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
-testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.dtb.write_hits                       3935                       # DTB write hits
-testsys.cpu.dtb.write_misses                        0                       # DTB write misses
-testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
-testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.dtb.data_hits                       11000                       # DTB hits
-testsys.cpu.dtb.data_misses                         0                       # DTB misses
-testsys.cpu.dtb.data_acv                            0                       # DTB access violations
-testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
-testsys.cpu.itb.fetch_hits                       5992                       # ITB hits
-testsys.cpu.itb.fetch_misses                        0                       # ITB misses
-testsys.cpu.itb.fetch_acv                           0                       # ITB acv
-testsys.cpu.itb.fetch_accesses                   5992                       # ITB accesses
-testsys.cpu.itb.read_hits                           0                       # DTB read hits
-testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.write_hits                          0                       # DTB write hits
-testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.numPwrStateTransitions                 80                       # Number of power state transitions
-testsys.cpu.pwrStateClkGateDist::samples           41                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::mean    9495085.365854                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::stdev   1417220.659876                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::1000-5e+10           41    100.00%    100.00% # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::min_value      2964500                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::max_value      9815000                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateClkGateDist::total             41                       # Distribution of time spent in the clock gated state
-testsys.cpu.pwrStateResidencyTicks::ON       18043000                       # Cumulative time (in ticks) in various power states
-testsys.cpu.pwrStateResidencyTicks::CLK_GATED    389298500                       # Cumulative time (in ticks) in various power states
-testsys.cpu.numCycles                          821056                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                  0                      
-testsys.cpu.kern.mode_good::user                    0                      
-testsys.cpu.kern.mode_good::idle                    0                      
-testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
-testsys.cpu.committedInsts                      36126                       # Number of instructions committed
-testsys.cpu.committedOps                        36126                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses                33492                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
-testsys.cpu.num_func_calls                       2384                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts         2346                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                       33492                       # number of integer instructions
-testsys.cpu.num_fp_insts                            0                       # number of float instructions
-testsys.cpu.num_int_register_reads              43747                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes             26476                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                        11041                       # number of memory refs
-testsys.cpu.num_load_insts                       7105                       # Number of load instructions
-testsys.cpu.num_store_insts                      3936                       # Number of store instructions
-testsys.cpu.num_idle_cycles              784687.711054                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              36368.288946                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.044295                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.955705                       # Percentage of idle cycles
-testsys.cpu.Branches                             5238                       # Number of branches fetched
-testsys.cpu.op_class::No_OpClass                 1261      3.49%      3.49% # Class of executed instruction
-testsys.cpu.op_class::IntAlu                    21664     59.97%     63.46% # Class of executed instruction
-testsys.cpu.op_class::IntMult                      44      0.12%     63.58% # Class of executed instruction
-testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatMult                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatMultAcc                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatMisc                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMult                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShift                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::MemRead                    7674     21.24%     84.82% # Class of executed instruction
-testsys.cpu.op_class::MemWrite                   3938     10.90%     95.72% # Class of executed instruction
-testsys.cpu.op_class::FloatMemRead                  0      0.00%     95.72% # Class of executed instruction
-testsys.cpu.op_class::FloatMemWrite                 0      0.00%     95.72% # Class of executed instruction
-testsys.cpu.op_class::IprAccess                  1545      4.28%    100.00% # Class of executed instruction
-testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-testsys.cpu.op_class::total                     36126                       # Class of executed instruction
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.iobridge.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.iobus.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.iobus.trans_dist::ReadReq                5049                       # Transaction distribution
-testsys.iobus.trans_dist::ReadResp               5049                       # Transaction distribution
-testsys.iobus.trans_dist::WriteReq                 81                       # Transaction distribution
-testsys.iobus.trans_dist::WriteResp                81                       # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave         9698                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total         9698                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total                  10260                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total                  118304                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoop_filter.tot_requests            0                       # Total number of requests made to the snoop filter.
-testsys.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-testsys.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-testsys.membus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
-testsys.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-testsys.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-testsys.membus.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.membus.trans_dist::ReadReq              47876                       # Transaction distribution
-testsys.membus.trans_dist::ReadResp             48080                       # Transaction distribution
-testsys.membus.trans_dist::WriteReq              3691                       # Transaction distribution
-testsys.membus.trans_dist::WriteResp             3691                       # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq           204                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port        72252                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total        72252                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port        21438                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total        22000                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port         9698                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total         9698                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total                103950                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port       144504                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total       144504                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total                 340448                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops                               0                       # Total snoops (count)
-testsys.membus.snoopTraffic                         0                       # Total snoop traffic (bytes)
-testsys.membus.snoop_fanout::samples            51975                       # Request fanout histogram
-testsys.membus.snoop_fanout::mean                   0                       # Request fanout histogram
-testsys.membus.snoop_fanout::stdev                  0                       # Request fanout histogram
-testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0                  51975    100.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::max_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::total              51975                       # Request fanout histogram
-testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ethernet.descDMAReads            4849                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes       116376                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle              40                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle             4849                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts         4849                       # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED    407341500                       # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
deleted file mode 100644
index b0d37ba..0000000
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
+++ /dev/null
Binary files differ
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
deleted file mode 100644
index fcd6df1..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ /dev/null
@@ -1,877 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
deleted file mode 100755
index bbcd9d7..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr
+++ /dev/null
@@ -1,3 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
deleted file mode 100755
index 321da6b..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:43
-gem5 executing on e108600-lin, pid 28041
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 41083000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
deleted file mode 100644
index 879f020..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ /dev/null
@@ -1,763 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000041                       # Number of seconds simulated
-sim_ticks                                    41083000                       # Number of ticks simulated
-final_tick                                   41083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 202272                       # Simulator instruction rate (inst/s)
-host_op_rate                                   202193                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1294825774                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252636                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                        6413                       # Number of instructions simulated
-sim_ops                                          6413                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             23232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34048                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23232                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                363                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   532                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            565489375                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            263271913                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               828761288                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       565489375                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          565489375                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           565489375                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           263271913                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              828761288                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           532                       # Number of read requests accepted
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         532                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    34048                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     34048                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  73                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  36                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  54                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  45                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  21                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                   5                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 21                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 29                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 19                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                127                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 47                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 14                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        40972000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     532                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           91                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      363.604396                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     235.588514                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     321.826485                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             22     24.18%     24.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           22     24.18%     48.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           13     14.29%     62.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8      8.79%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            5      5.49%     76.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      4.40%     81.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      3.30%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            8      8.79%     93.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      6.59%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             91                       # Bytes accessed per row activation
-system.physmem.totQLat                        6584250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  16559250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2660000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12376.41                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31126.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         828.76                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      828.76                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.47                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       6.47                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        436                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        77015.04                       # Average gap between requests
-system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     264180                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     136620                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1956360                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                3932430                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  68640                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy          13617300                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy            928800                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy                 23977530                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              583.625643                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime               32009500                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE          39500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF         1300000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN      2418500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT         7463000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN     29862000                       # Time in different power states
-system.physmem_1.actEnergy                     421260                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     208725                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1842120                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3073200.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                4023060                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 174720                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy          14292180                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy            178080                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy                 24213345                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              589.365503                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime               31744250                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE         288500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF         1300000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN       464250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT         7679500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN     31350750                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2002                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1237                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               378                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1602                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     377                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             23.533084                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     234                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             333                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                 14                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              319                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          114                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1365                       # DTB read hits
-system.cpu.dtb.read_misses                         11                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1376                       # DTB read accesses
-system.cpu.dtb.write_hits                         884                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     887                       # DTB write accesses
-system.cpu.dtb.data_hits                         2249                       # DTB hits
-system.cpu.dtb.data_misses                         14                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2263                       # DTB accesses
-system.cpu.itb.fetch_hits                        2685                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2702                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            82166                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6413                       # Number of instructions committed
-system.cpu.committedOps                          6413                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1093                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              12.812412                       # CPI: cycles per instruction
-system.cpu.ipc                               0.078049                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass                  19      0.30%      0.30% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                    4331     67.53%     67.83% # Class of committed instruction
-system.cpu.op_class_0::IntMult                      1      0.02%     67.85% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                       0      0.00%     67.85% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd                     2      0.03%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatMult                    0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc                    0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc                0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.88% # Class of committed instruction
-system.cpu.op_class_0::MemRead                   1191     18.57%     86.45% # Class of committed instruction
-system.cpu.op_class_0::MemWrite                   861     13.43%     99.88% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead                 1      0.02%     99.89% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite                7      0.11%    100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                     6413                       # Class of committed instruction
-system.cpu.tickCycles                           12637                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           69529                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.987673                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1990                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.775148                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.987673                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025388                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025388                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4591                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4591                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1250                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1250                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1990                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1990                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1990                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1990                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           96                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            96                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          221                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            221                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          221                       # number of overall misses
-system.cpu.dcache.overall_misses::total           221                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8545500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8545500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     10428500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     10428500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     18974000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     18974000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     18974000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     18974000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1346                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1346                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2211                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2211                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2211                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2211                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.071322                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.071322                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099955                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099955                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.099955                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.099955                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        83428                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        83428                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 85855.203620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 85855.203620                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           52                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           52                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           52                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8449500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8449500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6089000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6089000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14538500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14538500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14538500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14538500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071322                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071322                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076436                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076436                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076436                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           175.158440                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2321                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               364                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.376374                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   175.158440                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085527                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085527                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.177734                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5734                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5734                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         2321                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2321                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2321                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2321                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2321                       # number of overall hits
-system.cpu.icache.overall_hits::total            2321                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           364                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            364                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          364                       # number of overall misses
-system.cpu.icache.overall_misses::total           364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     30321500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30321500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     30321500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30321500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     30321500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30321500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2685                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2685                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2685                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2685                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2685                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2685                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.135568                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.135568                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.135568                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.135568                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.135568                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.135568                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 83300.824176                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 83300.824176                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          364                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          364                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          364                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          364                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29957500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     29957500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29957500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     29957500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29957500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     29957500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135568                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.135568                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135568                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.135568                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          279.188916                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              532                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.001880                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.158050                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   104.030866                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005345                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003175                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.008520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          422                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.016235                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4796                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4796                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           96                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           96                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          363                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          169                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           532                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          363                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          532                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5979500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5979500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     29400000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     29400000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8304000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      8304000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     29400000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     14283500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     43683500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     29400000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     14283500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     43683500                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          364                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          364                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           96                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           96                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          364                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          169                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          533                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          364                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          169                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          533                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.997253                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.997253                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.997253                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.998124                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997253                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.998124                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        86500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        86500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          363                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           96                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           96                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          363                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          532                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          363                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5249500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5249500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     25770000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     25770000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7344000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7344000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     25770000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12593500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     38363500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     25770000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12593500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     38363500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.997253                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.998124                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997253                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.998124                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        76500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        76500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          533                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           460                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          364                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           96                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          728                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1066                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              34112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          533                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001876                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.043315                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                532     99.81%     99.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  1      0.19%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            533                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         266500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        546000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           532                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     41083000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                459                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           459                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   34048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               532                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     532    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 532                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              607000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2825000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              6.9                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
deleted file mode 100644
index 2a35cf8..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ /dev/null
@@ -1,873 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2 opList3 opList4
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList4]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1 opList2 opList3
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
deleted file mode 100755
index bbcd9d7..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
+++ /dev/null
@@ -1,3 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
deleted file mode 100755
index 06bbc9f..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Nov 29 2016 18:06:09
-gem5 started Nov 29 2016 18:06:29
-gem5 executing on zizzer, pid 27582
-command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 23776000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
deleted file mode 100644
index e679688..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000024                       # Number of seconds simulated
-sim_ticks                                    23776000                       # Number of ticks simulated
-final_tick                                   23776000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 135386                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135348                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              503875461                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253920                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-sim_insts                                        6385                       # Number of instructions simulated
-sim_ops                                          6385                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             19904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11072                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19904                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                311                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                173                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   484                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            837146703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            465679677                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1302826380                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       837146703                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          837146703                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           837146703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           465679677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1302826380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           484                       # Number of read requests accepted
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         484                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    30976                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     30976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  69                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  47                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  20                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                   3                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 22                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 25                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 14                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                118                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 45                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 13                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        23381000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     484                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       260                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       140                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        52                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           89                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      347.325843                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     230.027877                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     312.328054                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             21     23.60%     23.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           22     24.72%     48.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           15     16.85%     65.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            9     10.11%     75.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6      6.74%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      3.37%     85.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.25%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      1.12%     88.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     11.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             89                       # Bytes accessed per row activation
-system.physmem.totQLat                        8020750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  17095750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2420000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16571.80                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35321.80                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1302.83                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1302.83                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.18                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.18                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        48307.85                       # Average gap between requests
-system.physmem.pageHitRate                      81.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     242760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     125235                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1756440                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                3000480                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  47040                       # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy           7630020                       # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy            131040                       # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy                 14776935                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              621.499816                       # Core power per rank (mW)
-system.physmem_0.totalIdleTime               16971750                       # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE          40500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN       340500                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT         5886000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN     16729000                       # Time in different power states
-system.physmem_1.actEnergy                     399840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     212520                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1699320                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                2975400                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 130080                       # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy           7630590                       # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy             68640                       # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy                 14960310                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              629.212344                       # Core power per rank (mW)
-system.physmem_1.totalIdleTime               16765250                       # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE         214000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
-system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN       178500                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT         5879250                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN     16724250                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                    2851                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1679                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               484                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2196                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     719                       # Number of BTB hits
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.741348                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     442                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 42                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups             461                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits                 25                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses              436                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted          123                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2241                       # DTB read hits
-system.cpu.dtb.read_misses                         48                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2289                       # DTB read accesses
-system.cpu.dtb.write_hits                        1046                       # DTB write hits
-system.cpu.dtb.write_misses                        28                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1074                       # DTB write accesses
-system.cpu.dtb.data_hits                         3287                       # DTB hits
-system.cpu.dtb.data_misses                         76                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3363                       # DTB accesses
-system.cpu.itb.fetch_hits                        2298                       # ITB hits
-system.cpu.itb.fetch_misses                        27                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2325                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            47553                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8497                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16552                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2851                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1186                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          5772                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1050                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           656                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2298                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   338                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              15472                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.069804                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.455665                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    12480     80.66%     80.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      299      1.93%     82.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      231      1.49%     84.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      265      1.71%     85.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      295      1.91%     87.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      231      1.49%     89.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      280      1.81%     91.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      147      0.95%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1244      8.04%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                15472                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.059954                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.348075                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8344                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4012                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2454                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   211                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    451                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  754                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    75                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14992                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   221                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    451                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8504                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1836                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            655                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2480                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1546                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14425                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     21                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     10                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1479                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               10912                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17882                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17873                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  4577                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6335                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             22                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       586                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2823                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1299                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                17                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      13035                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  27                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10770                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                17                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6676                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3655                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             10                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         15472                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.696096                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.440906                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11426     73.85%     73.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1307      8.45%     82.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 919      5.94%     88.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 676      4.37%     92.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 515      3.33%     95.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 346      2.24%     98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 202      1.31%     99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  53      0.34%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  28      0.18%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           15472                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      21     14.79%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc                    0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     83     58.45%     73.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    37     26.06%     99.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead                 0      0.00%     99.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite                1      0.70%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7179     66.66%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2465     22.89%     89.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1113     10.33%     99.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead               1      0.01%     99.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite              7      0.06%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10770                       # Type of FU issued
-system.cpu.iq.rate                           0.226484                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         142                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013185                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              37150                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19749                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9744                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10899                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              119                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1638                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           23                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          434                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            78                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    451                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1424                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   338                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13146                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               125                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2823                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1299                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   331                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             23                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            110                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          389                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  499                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10283                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2289                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               487                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            84                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3373                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1639                       # Number of branches executed
-system.cpu.iew.exec_stores                       1084                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.216243                       # Inst execution rate
-system.cpu.iew.wb_sent                           9942                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9754                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5150                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7025                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.205118                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.733096                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts            6693                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               410                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        14238                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.449642                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.359190                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11808     82.93%     82.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1161      8.15%     91.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          469      3.29%     94.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          204      1.43%     95.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          134      0.94%     96.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           86      0.60%     97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           97      0.68%     98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           89      0.63%     98.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          190      1.33%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        14238                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 6402                       # Number of instructions committed
-system.cpu.commit.committedOps                   6402                       # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2050                       # Number of memory references committed
-system.cpu.commit.loads                          1185                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       1056                       # Number of branches committed
-system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      6319                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                  127                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu             4330     67.64%     67.93% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult               1      0.02%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc             0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.98% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead            1184     18.49%     86.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite            858     13.40%     99.88% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead            1      0.02%     99.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite            7      0.11%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total              6402                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   190                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        26792                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27441                       # The number of ROB writes
-system.cpu.timesIdled                             250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           32081                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        6385                       # Number of Instructions Simulated
-system.cpu.committedOps                          6385                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.447612                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.447612                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.134271                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.134271                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13028                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7426                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           110.199847                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2391                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               173                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.820809                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   110.199847                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026904                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026904                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          173                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.042236                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              6029                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             6029                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1883                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1883                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          508                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            508                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2391                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2391                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2391                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2391                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          180                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           180                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          357                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          357                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          537                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            537                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          537                       # number of overall misses
-system.cpu.dcache.overall_misses::total           537                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     13954000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     13954000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     31258982                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     31258982                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     45212982                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     45212982                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     45212982                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     45212982                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2063                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2063                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2928                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2928                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2928                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2928                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.087252                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.087252                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.412717                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.412717                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.183402                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.183402                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.183402                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.183402                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 84195.497207                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 84195.497207                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         3108                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                37                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           84                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           79                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          285                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          285                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          364                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          364                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          364                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          364                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9402500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      9402500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7030000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7030000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     16432500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     16432500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     16432500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     16432500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048958                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048958                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059085                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059085                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.059085                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.059085                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           160.011089                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1840                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               312                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.897436                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   160.011089                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078130                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078130                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          312                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          186                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.152344                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4908                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4908                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         1840                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1840                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1840                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1840                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1840                       # number of overall hits
-system.cpu.icache.overall_hits::total            1840                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          458                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           458                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          458                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            458                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          458                       # number of overall misses
-system.cpu.icache.overall_misses::total           458                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     35481000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     35481000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     35481000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     35481000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     35481000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     35481000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2298                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2298                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2298                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2298                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2298                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2298                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199304                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.199304                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.199304                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.199304                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.199304                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.199304                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77469.432314                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77469.432314                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77469.432314                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77469.432314                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77469.432314                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77469.432314                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          146                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          146                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          146                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          146                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          146                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          146                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          312                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          312                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          312                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          312                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26195000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26195000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26195000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26195000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26195000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26195000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.135770                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.135770                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.135770                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.135770                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.135770                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.135770                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83958.333333                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83958.333333                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83958.333333                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83958.333333                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83958.333333                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83958.333333                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          270.308724                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              484                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002066                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.032476                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   110.276248                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004884                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003365                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.008249                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          484                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014771                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4364                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4364                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           72                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           72                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          311                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          311                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          101                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          101                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          311                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          173                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           484                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          311                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          173                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          484                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6919000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6919000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25713500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25713500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      9242500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      9242500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25713500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     16161500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     41875000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25713500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     16161500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     41875000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           72                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           72                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          312                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          312                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          312                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          173                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          485                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          312                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          173                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          485                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996795                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996795                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996795                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997938                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996795                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997938                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 86518.595041                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 86518.595041                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          311                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          311                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          101                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          101                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          311                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          484                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          311                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          484                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6199000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      6199000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22603500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22603500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      8232500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      8232500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22603500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     14431500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     37035000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22603500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     14431500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     37035000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996795                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997938                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997938                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          485                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          312                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          624                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               970                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              31040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          485                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.002062                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.045408                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                484     99.79%     99.79% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  1      0.21%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            485                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         242500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        468000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        259500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           484                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     23776000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                412                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           412                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          968                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    968                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   30976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               484                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     484    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 484                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              593000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2566000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             10.8                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
deleted file mode 100644
index c117163..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,203 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
deleted file mode 100755
index aadc3d0..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
deleted file mode 100755
index a049bb5..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39609
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 3214500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
deleted file mode 100644
index f9588e6..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,167 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     3214500                       # Number of ticks simulated
-final_tick                                    3214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1072411                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1070683                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              536687952                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241476                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        6403                       # Number of instructions simulated
-sim_ops                                          6403                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED      3214500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             25652                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34456                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25652                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25652                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
-system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6413                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7598                       # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7980090216                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2738839633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10718929849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7980090216                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7980090216                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          2083061129                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2083061129                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7980090216                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4821900762                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            12801990978                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED      3214500                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
-system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.write_hits                         865                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6413                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6430                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON         3214500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                             6430                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6403                       # Number of instructions committed
-system.cpu.committedOps                          6403                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6329                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          754                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6329                       # number of integer instructions
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8297                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4575                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       6430                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                              1056                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      4331     67.53%     67.83% # Class of executed instruction
-system.cpu.op_class::IntMult                        1      0.02%     67.85% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     67.85% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::MemRead                     1191     18.57%     86.45% # Class of executed instruction
-system.cpu.op_class::MemWrite                     861     13.43%     99.88% # Class of executed instruction
-system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       6413                       # Class of executed instruction
-system.membus.snoop_filter.tot_requests             0                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED      3214500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7598                       # Transaction distribution
-system.membus.trans_dist::ReadResp               7598                       # Transaction distribution
-system.membus.trans_dist::WriteReq                865                       # Transaction distribution
-system.membus.trans_dist::WriteResp               865                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port        12826                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         4100                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  16926                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        25652                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port        15500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   41152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples              8463                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    8463    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                8463                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
deleted file mode 100644
index 6b91b5d..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ /dev/null
@@ -1,1266 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu.clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=5
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=12
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=4
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
-buffer_size=0
-cacheMemory=system.ruby.l1_cntrl0.cacheMemory
-cache_response_latency=12
-clk_domain=system.cpu.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl0.forwardToCache
-issue_latency=2
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl0.requestFromCache
-responseFromCache=system.ruby.l1_cntrl0.responseFromCache
-responseToCache=system.ruby.l1_cntrl0.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l1_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.cpu.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.cacheMemory
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.cacheMemory
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
-netifs=
-number_of_virtual_networks=5
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers36]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers37]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers38]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers39]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers2
-eventq_index=0
-latency=1
-link_id=2
-src_node=system.ruby.network.routers0
-src_outport=
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers2
-eventq_index=0
-latency=1
-link_id=3
-src_node=system.ruby.network.routers1
-src_outport=
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers0
-eventq_index=0
-latency=1
-link_id=4
-src_node=system.ruby.network.routers2
-src_outport=
-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers1
-eventq_index=0
-latency=1
-link_id=5
-src_node=system.ruby.network.routers2
-src_outport=
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
-power_model=Null
-router_id=0
-virt_nets=5
-
-[system.ruby.network.routers0.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
-power_model=Null
-router_id=1
-virt_nets=5
-
-[system.ruby.network.routers1.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
-power_model=Null
-router_id=2
-virt_nets=5
-
-[system.ruby.network.routers2.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
deleted file mode 100755
index f6f6f15..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ /dev/null
@@ -1,10 +0,0 @@
-warn: rounding error > tolerance
-    1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
-warn: rounding error > tolerance
-    1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
deleted file mode 100755
index 89adb8b..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:45
-gem5 executing on e108600-lin, pid 28066
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 112490 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
deleted file mode 100644
index 639ae90..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ /dev/null
@@ -1,702 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000112                       # Number of seconds simulated
-sim_ticks                                      112490                       # Number of ticks simulated
-final_tick                                     112490                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109524                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109501                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1923375                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 415960                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-sim_insts                                        6403                       # Number of instructions simulated
-sim_ops                                          6403                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                             1                       # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0       110784                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total             110784                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0       110528                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total          110528                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0         1731                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total                1731                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0         1727                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total               1727                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0    984834207                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total             984834207                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0    982558450                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total            982558450                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0   1967392657                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total           1967392657                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                        1731                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                       1727                       # Number of write requests accepted
-system.mem_ctrls.readBursts                      1731                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                     1727                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM                  56704                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   54080                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                   57088                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                  110784                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys               110528                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    845                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   803                       # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0                83                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1                50                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2                70                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3                63                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4               108                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5                23                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10               55                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11               36                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12               18                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13              270                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14               81                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15               24                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0                82                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1                51                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2                73                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3                60                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4               126                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5                27                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9                 1                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10               50                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11               33                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12               12                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13              268                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14               81                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15               24                       # Per bank write bursts
-system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                        112412                       # Total gap between requests
-system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                  1731                       # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6                 1727                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                     886                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                     51                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                     60                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                     57                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                     56                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                     55                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples          264                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean           424                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   260.079273                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   372.426347                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           66     25.00%     25.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           58     21.97%     46.97% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           27     10.23%     57.20% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           16      6.06%     63.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639           17      6.44%     69.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767            8      3.03%     72.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895           12      4.55%     77.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023           10      3.79%     81.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151           50     18.94%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total          264                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples           55                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      15.818182                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean     15.638991                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev      2.938196                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13             3      5.45%      5.45% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15            24     43.64%     49.09% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17            23     41.82%     90.91% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19             4      7.27%     98.18% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35             1      1.82%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total            55                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples           55                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      16.218182                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     16.206001                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      0.658025                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16               49     89.09%     89.09% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                1      1.82%     90.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18                4      7.27%     98.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19                1      1.82%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total            55                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                        16225                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat                   33059                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                       4430                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                        18.31                       # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                   37.31                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                       504.08                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                       507.49                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                    984.83                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                    982.56                       # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil                         7.90                       # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead                     3.94                       # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite                    3.96                       # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      26.10                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                      674                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                     833                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 76.07                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                90.15                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                         32.51                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    83.26                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                   735420                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                   386400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy                 4581024                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy                3532896                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy             13923048                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy               195072                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy        30921360                       # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy         5237376                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy               68117556                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            605.543213                       # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime                81406                       # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE           88                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN        13639                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT         27313                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN        67810                       # Time in different power states
-system.mem_ctrls_1.actEnergy                  1199520                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                   633696                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy                 5540640                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy                3917088                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy             12524952                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy               314880                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy        33139344                       # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy         4427136                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy               70302216                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            624.964139                       # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime                83983                       # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE          260                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN        11529                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT         24387                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN        72674                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
-system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.write_hits                         865                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6414                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6431                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON          112490                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           112490                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6403                       # Number of instructions committed
-system.cpu.committedOps                          6403                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6329                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          754                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6329                       # number of integer instructions
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8297                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4575                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     112490                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                              1056                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      4331     67.53%     67.83% # Class of executed instruction
-system.cpu.op_class::IntMult                        1      0.02%     67.85% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     67.85% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::MemRead                     1191     18.57%     86.45% # Class of executed instruction
-system.cpu.op_class::MemWrite                     861     13.43%     99.88% # Class of executed instruction
-system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       6413                       # Class of executed instruction
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   3458                       # delay histogram for all message
-system.ruby.delayHist                    |        3458    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     3458                       # delay histogram for all message
-system.ruby.outstanding_req_hist_seqr::bucket_size            1                      
-system.ruby.outstanding_req_hist_seqr::max_bucket            9                      
-system.ruby.outstanding_req_hist_seqr::samples         8464                      
-system.ruby.outstanding_req_hist_seqr::mean            1                      
-system.ruby.outstanding_req_hist_seqr::gmean            1                      
-system.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |        8464    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist_seqr::total         8464                      
-system.ruby.latency_hist_seqr::bucket_size           64                      
-system.ruby.latency_hist_seqr::max_bucket          639                      
-system.ruby.latency_hist_seqr::samples           8463                      
-system.ruby.latency_hist_seqr::mean         12.291977                      
-system.ruby.latency_hist_seqr::gmean         2.221869                      
-system.ruby.latency_hist_seqr::stdev        27.407806                      
-system.ruby.latency_hist_seqr            |        7608     89.90%     89.90% |         798      9.43%     99.33% |          40      0.47%     99.80% |           5      0.06%     99.86% |           6      0.07%     99.93% |           6      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist_seqr::total             8463                      
-system.ruby.hit_latency_hist_seqr::bucket_size            1                      
-system.ruby.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.hit_latency_hist_seqr::samples         6732                      
-system.ruby.hit_latency_hist_seqr::mean             1                      
-system.ruby.hit_latency_hist_seqr::gmean            1                      
-system.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |        6732    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist_seqr::total         6732                      
-system.ruby.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.miss_latency_hist_seqr::max_bucket          639                      
-system.ruby.miss_latency_hist_seqr::samples         1731                      
-system.ruby.miss_latency_hist_seqr::mean    56.207395                      
-system.ruby.miss_latency_hist_seqr::gmean    49.560362                      
-system.ruby.miss_latency_hist_seqr::stdev    35.333412                      
-system.ruby.miss_latency_hist_seqr       |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist_seqr::total         1731                      
-system.ruby.Directory.incomplete_times_seqr         1730                      
-system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time     0.997813                       # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time    11.743091                       # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time     0.999387                       # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time     0.999396                       # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.cacheMemory.demand_hits         6732                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses         1731                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8463                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.l1_cntrl0.forwardToCache.avg_stall_time     6.984319                       # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs     0.075242                       # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time     0.999991                       # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs     0.061480                       # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromCache.avg_stall_time     1.999947                       # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToCache.avg_stall_time     6.995333                       # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time     5.986612                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers04.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers04.avg_stall_time     5.996053                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers07.avg_buf_msgs     0.092150                       # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers07.avg_stall_time     6.743802                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized     7.685128                      
-system.ruby.network.routers0.msg_count.Control::2         1731                      
-system.ruby.network.routers0.msg_count.Data::2         1727                      
-system.ruby.network.routers0.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers0.msg_bytes.Control::2        13848                      
-system.ruby.network.routers0.msg_bytes.Data::2       124344                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time    10.743268                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers06.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers06.avg_stall_time     1.995609                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers07.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers07.avg_stall_time     1.998755                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized     7.685128                      
-system.ruby.network.routers1.msg_count.Control::2         1731                      
-system.ruby.network.routers1.msg_count.Data::2         1727                      
-system.ruby.network.routers1.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers1.msg_bytes.Control::2        13848                      
-system.ruby.network.routers1.msg_bytes.Data::2       124344                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.int_link_buffers02.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time     7.743695                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers08.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers08.avg_stall_time     2.993386                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers09.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers09.avg_stall_time     2.998107                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers13.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers13.avg_stall_time     4.988888                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers14.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers14.avg_stall_time     4.996755                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers17.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.network.int_link_buffers17.avg_stall_time     9.743428                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs     0.015352                       # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time     3.991146                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs     0.015388                       # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time     3.997440                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers07.avg_buf_msgs     0.030740                       # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers07.avg_stall_time     8.743571                       # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized     7.685128                      
-system.ruby.network.routers2.msg_count.Control::2         1731                      
-system.ruby.network.routers2.msg_count.Data::2         1727                      
-system.ruby.network.routers2.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers2.msg_bytes.Control::2        13848                      
-system.ruby.network.routers2.msg_bytes.Data::2       124344                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control            5193                      
-system.ruby.network.msg_count.Data               5181                      
-system.ruby.network.msg_count.Response_Data         5193                      
-system.ruby.network.msg_count.Writeback_Control         5181                      
-system.ruby.network.msg_byte.Control            41544                      
-system.ruby.network.msg_byte.Data              373032                      
-system.ruby.network.msg_byte.Response_Data       373896                      
-system.ruby.network.msg_byte.Writeback_Control        41448                      
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization     7.692239                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers0.throttle1.link_utilization     7.678016                      
-system.ruby.network.routers0.throttle1.msg_count.Control::2         1731                      
-system.ruby.network.routers0.throttle1.msg_count.Data::2         1727                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2        13848                      
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2       124344                      
-system.ruby.network.routers1.throttle0.link_utilization     7.678016                      
-system.ruby.network.routers1.throttle0.msg_count.Control::2         1731                      
-system.ruby.network.routers1.throttle0.msg_count.Data::2         1727                      
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2        13848                      
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2       124344                      
-system.ruby.network.routers1.throttle1.link_utilization     7.692239                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers2.throttle0.link_utilization     7.692239                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1731                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1727                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       124632                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        13816                      
-system.ruby.network.routers2.throttle1.link_utilization     7.678016                      
-system.ruby.network.routers2.throttle1.msg_count.Control::2         1731                      
-system.ruby.network.routers2.throttle1.msg_count.Data::2         1727                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2        13848                      
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2       124344                      
-system.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples          1731                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |        1731    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total            1731                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples          1727                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |        1727    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total            1727                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size           64                      
-system.ruby.LD.latency_hist_seqr::max_bucket          639                      
-system.ruby.LD.latency_hist_seqr::samples         1185                      
-system.ruby.LD.latency_hist_seqr::mean      33.356118                      
-system.ruby.LD.latency_hist_seqr::gmean     10.708915                      
-system.ruby.LD.latency_hist_seqr::stdev     36.387225                      
-system.ruby.LD.latency_hist_seqr         |         862     72.74%     72.74% |         301     25.40%     98.14% |          16      1.35%     99.49% |           3      0.25%     99.75% |           1      0.08%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist_seqr::total          1185                      
-system.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
-system.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.LD.hit_latency_hist_seqr::samples          457                      
-system.ruby.LD.hit_latency_hist_seqr::mean            1                      
-system.ruby.LD.hit_latency_hist_seqr::gmean            1                      
-system.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         457    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist_seqr::total          457                      
-system.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
-system.ruby.LD.miss_latency_hist_seqr::samples          728                      
-system.ruby.LD.miss_latency_hist_seqr::mean    53.667582                      
-system.ruby.LD.miss_latency_hist_seqr::gmean    47.442261                      
-system.ruby.LD.miss_latency_hist_seqr::stdev    32.940895                      
-system.ruby.LD.miss_latency_hist_seqr    |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist_seqr::total          728                      
-system.ruby.ST.latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.latency_hist_seqr::max_bucket          319                      
-system.ruby.ST.latency_hist_seqr::samples          865                      
-system.ruby.ST.latency_hist_seqr::mean      17.479769                      
-system.ruby.ST.latency_hist_seqr::gmean      3.361529                      
-system.ruby.ST.latency_hist_seqr::stdev     31.340829                      
-system.ruby.ST.latency_hist_seqr         |         592     68.44%     68.44% |         160     18.50%     86.94% |         102     11.79%     98.73% |           0      0.00%     98.73% |           4      0.46%     99.19% |           4      0.46%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00%
-system.ruby.ST.latency_hist_seqr::total           865                      
-system.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
-system.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.ST.hit_latency_hist_seqr::samples          592                      
-system.ruby.ST.hit_latency_hist_seqr::mean            1                      
-system.ruby.ST.hit_latency_hist_seqr::gmean            1                      
-system.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         592    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist_seqr::total          592                      
-system.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
-system.ruby.ST.miss_latency_hist_seqr::samples          273                      
-system.ruby.ST.miss_latency_hist_seqr::mean    53.216117                      
-system.ruby.ST.miss_latency_hist_seqr::gmean    46.594106                      
-system.ruby.ST.miss_latency_hist_seqr::stdev    35.315815                      
-system.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
-system.ruby.ST.miss_latency_hist_seqr::total          273                      
-system.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.latency_hist_seqr::samples         6413                      
-system.ruby.IFETCH.latency_hist_seqr::mean     7.699984                      
-system.ruby.IFETCH.latency_hist_seqr::gmean     1.571280                      
-system.ruby.IFETCH.latency_hist_seqr::stdev    22.534194                      
-system.ruby.IFETCH.latency_hist_seqr     |        5994     93.47%     93.47% |         395      6.16%     99.63% |          16      0.25%     99.88% |           1      0.02%     99.89% |           3      0.05%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist_seqr::total         6413                      
-system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
-system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist_seqr::samples         5683                      
-system.ruby.IFETCH.hit_latency_hist_seqr::mean            1                      
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
-system.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |        5683    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total         5683                      
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.miss_latency_hist_seqr::samples          730                      
-system.ruby.IFETCH.miss_latency_hist_seqr::mean    59.858904                      
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean    52.975537                      
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev    37.310775                      
-system.ruby.IFETCH.miss_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total          730                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples         1731                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean    56.207395                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean    49.560362                      
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev    35.333412                      
-system.ruby.Directory.miss_mach_latency_hist_seqr |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total         1731                      
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples            1                      
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev          nan                      
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total            1                      
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size            1                      
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples            1                      
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev          nan                      
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total            1                      
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size            1                      
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket            9                      
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples            1                      
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev          nan                      
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total            1                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size            8                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket           79                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples            1                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean           75                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean    75.000000                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev          nan                      
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
-system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total            1                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          728                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    53.667582                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    47.442261                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    32.940895                      
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          728                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          273                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    53.216117                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    46.594106                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    35.315815                      
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          273                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          730                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    59.858904                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    52.975537                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    37.310775                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          730                      
-system.ruby.Directory_Controller.GETX            1731      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX            1727      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1731      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack         1727      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX          1731      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX          1727      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data         1731      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack         1727      0.00%      0.00%
-system.ruby.L1Cache_Controller.Load              1185      0.00%      0.00%
-system.ruby.L1Cache_Controller.Ifetch            6413      0.00%      0.00%
-system.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
-system.ruby.L1Cache_Controller.Data              1731      0.00%      0.00%
-system.ruby.L1Cache_Controller.Replacement         1727      0.00%      0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack         1727      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Load             728      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Ifetch           730      0.00%      0.00%
-system.ruby.L1Cache_Controller.I.Store            273      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Load             457      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Ifetch          5683      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Store            592      0.00%      0.00%
-system.ruby.L1Cache_Controller.M.Replacement         1727      0.00%      0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack         1727      0.00%      0.00%
-system.ruby.L1Cache_Controller.IS.Data           1458      0.00%      0.00%
-system.ruby.L1Cache_Controller.IM.Data            273      0.00%      0.00%
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
deleted file mode 100644
index d2de156..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,366 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
deleted file mode 100755
index aadc3d0..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
deleted file mode 100755
index 7b601db..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ /dev/null
@@ -1,15 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:28
-gem5 executing on e108600-lin, pid 39614
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 35682500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
deleted file mode 100644
index e0ad70e..0000000
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,525 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000036                       # Number of seconds simulated
-sim_ticks                                    36128500                       # Number of ticks simulated
-final_tick                                   36128500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 739000                       # Simulator instruction rate (inst/s)
-host_op_rate                                   738191                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4160971439                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251728                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        6403                       # Number of instructions simulated
-sim_ops                                          6403                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            492464398                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            297604384                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               790068782                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       492464398                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          492464398                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           492464398                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           297604384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              790068782                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
-system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.write_hits                         865                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6414                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6431                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            72257                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6403                       # Number of instructions committed
-system.cpu.committedOps                          6403                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6329                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          754                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6329                       # number of integer instructions
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8297                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4575                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      72257                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                              1056                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu                      4331     67.53%     67.83% # Class of executed instruction
-system.cpu.op_class::IntMult                        1      0.02%     67.85% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     67.85% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.88% # Class of executed instruction
-system.cpu.op_class::MemRead                     1191     18.57%     86.45% # Class of executed instruction
-system.cpu.op_class::MemWrite                     861     13.43%     99.88% # Class of executed instruction
-system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       6413                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.721081                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1882                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.202381                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.721081                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025323                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025323                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.041016                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4268                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4268                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1090                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1090                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1882                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1882                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1882                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1882                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           73                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
-system.cpu.dcache.overall_misses::total           168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5985000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5985000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4599000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4599000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     10584000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     10584000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     10584000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     10584000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080169                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.080169                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.081951                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081951                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.081951                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081951                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        63000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        63000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        63000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        63000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        63000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        63000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        63000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        63000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5890000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5890000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4526000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4526000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10416000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10416000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10416000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10416000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        62000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        62000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        62000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        62000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           127.170991                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                6135                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             21.989247                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   127.170991                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.062095                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.062095                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.136230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             13107                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            13107                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         6135                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6135                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6135                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6135                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6135                       # number of overall hits
-system.cpu.icache.overall_hits::total            6135                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           279                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          279                       # number of overall misses
-system.cpu.icache.overall_misses::total           279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17528500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17528500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17528500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17528500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17528500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17528500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6414                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6414                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6414                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6414                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6414                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6414                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043499                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.043499                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.043499                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.043499                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.043499                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.043499                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62826.164875                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62826.164875                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17249500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     17249500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17249500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     17249500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17249500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     17249500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043499                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.043499                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.043499                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          230.937880                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              446                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002242                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.167974                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   103.769906                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003881                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003167                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007048                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          446                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013611                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4022                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4022                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           95                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           95                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4416500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4416500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16819500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     16819500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5747500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5747500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16819500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10164000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     26983500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16819500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10164000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     26983500                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          279                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          279                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           95                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           95                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996416                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        60500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        60500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        60500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        60500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           95                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           95                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3686500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3686500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14039500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14039500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4797500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4797500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14039500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8484000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     22523500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14039500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8484000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     22523500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996416                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        50500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076                       # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests          447                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp           374                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           95                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          336                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               894                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples          447                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.002237                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.047298                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                446     99.78%     99.78% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  1      0.22%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            447                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         223500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        418500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        252000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.membus.snoop_filter.tot_requests           446                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                373                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           373                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               446                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     446    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 446                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              446500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2230000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
deleted file mode 100644
index d465f33..0000000
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ /dev/null
@@ -1,908 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=true
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cacheStorePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts0 system.cpu.interrupts1
-isa=system.cpu.isa0 system.cpu.isa1
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload0 system.cpu.workload1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=2
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2 opList3 opList4
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMultAcc
-opLat=5
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMisc
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList4]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList4.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1 opList2 opList3
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList3]
-type=OpDesc
-eventq_index=0
-opClass=FloatMemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts0]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.interrupts1]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa0]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.isa1]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload0]
-type=Process
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu.workload1]
-type=Process
-cmd=hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=101
-ppid=100
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
deleted file mode 100755
index b1d1f26..0000000
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
+++ /dev/null
@@ -1,7 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: Already in the requested power state, request ignored
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
deleted file mode 100755
index 45d42fd..0000000
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
+++ /dev/null
@@ -1,14 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 21:52:42
-gem5 started Mar 29 2017 21:52:53
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 118268
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
-
-Global frequency set at 1000000000000 ticks per second
-Hello world!
-Hello world!
-Exiting @ tick 27117500 because exiting with last active thread context
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
deleted file mode 100644
index 1efa6d7..0000000
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ /dev/null
@@ -1,1185 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000027                      
-sim_ticks                                    27117500                      
-final_tick                                   27117500                      
-sim_freq                                 1000000000000                      
-host_inst_rate                                 121145                      
-host_op_rate                                   121128                      
-host_tick_rate                              257188425                      
-host_mem_usage                                 265776                      
-host_seconds                                     0.11                      
-sim_insts                                       12770                      
-sim_ops                                         12770                      
-system.voltage_domain.voltage                       1                      
-system.clk_domain.clock                          1000                      
-system.physmem.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.physmem.bytes_read::cpu.inst             39680                      
-system.physmem.bytes_read::cpu.data             21888                      
-system.physmem.bytes_read::total                61568                      
-system.physmem.bytes_inst_read::cpu.inst        39680                      
-system.physmem.bytes_inst_read::total           39680                      
-system.physmem.num_reads::cpu.inst                620                      
-system.physmem.num_reads::cpu.data                342                      
-system.physmem.num_reads::total                   962                      
-system.physmem.bw_read::cpu.inst           1463261731                      
-system.physmem.bw_read::cpu.data            807154052                      
-system.physmem.bw_read::total              2270415783                      
-system.physmem.bw_inst_read::cpu.inst      1463261731                      
-system.physmem.bw_inst_read::total         1463261731                      
-system.physmem.bw_total::cpu.inst          1463261731                      
-system.physmem.bw_total::cpu.data           807154052                      
-system.physmem.bw_total::total             2270415783                      
-system.physmem.readReqs                           963                      
-system.physmem.writeReqs                            0                      
-system.physmem.readBursts                         963                      
-system.physmem.writeBursts                          0                      
-system.physmem.bytesReadDRAM                    61632                      
-system.physmem.bytesReadWrQ                         0                      
-system.physmem.bytesWritten                         0                      
-system.physmem.bytesReadSys                     61632                      
-system.physmem.bytesWrittenSys                      0                      
-system.physmem.servicedByWrQ                        0                      
-system.physmem.mergedWrBursts                       0                      
-system.physmem.neitherReadNorWriteReqs              0                      
-system.physmem.perBankRdBursts::0                  82                      
-system.physmem.perBankRdBursts::1                 150                      
-system.physmem.perBankRdBursts::2                  77                      
-system.physmem.perBankRdBursts::3                  59                      
-system.physmem.perBankRdBursts::4                  88                      
-system.physmem.perBankRdBursts::5                  45                      
-system.physmem.perBankRdBursts::6                  32                      
-system.physmem.perBankRdBursts::7                  50                      
-system.physmem.perBankRdBursts::8                  42                      
-system.physmem.perBankRdBursts::9                  38                      
-system.physmem.perBankRdBursts::10                 28                      
-system.physmem.perBankRdBursts::11                 33                      
-system.physmem.perBankRdBursts::12                 15                      
-system.physmem.perBankRdBursts::13                120                      
-system.physmem.perBankRdBursts::14                 67                      
-system.physmem.perBankRdBursts::15                 37                      
-system.physmem.perBankWrBursts::0                   0                      
-system.physmem.perBankWrBursts::1                   0                      
-system.physmem.perBankWrBursts::2                   0                      
-system.physmem.perBankWrBursts::3                   0                      
-system.physmem.perBankWrBursts::4                   0                      
-system.physmem.perBankWrBursts::5                   0                      
-system.physmem.perBankWrBursts::6                   0                      
-system.physmem.perBankWrBursts::7                   0                      
-system.physmem.perBankWrBursts::8                   0                      
-system.physmem.perBankWrBursts::9                   0                      
-system.physmem.perBankWrBursts::10                  0                      
-system.physmem.perBankWrBursts::11                  0                      
-system.physmem.perBankWrBursts::12                  0                      
-system.physmem.perBankWrBursts::13                  0                      
-system.physmem.perBankWrBursts::14                  0                      
-system.physmem.perBankWrBursts::15                  0                      
-system.physmem.numRdRetry                           0                      
-system.physmem.numWrRetry                           0                      
-system.physmem.totGap                        27086500                      
-system.physmem.readPktSize::0                       0                      
-system.physmem.readPktSize::1                       0                      
-system.physmem.readPktSize::2                       0                      
-system.physmem.readPktSize::3                       0                      
-system.physmem.readPktSize::4                       0                      
-system.physmem.readPktSize::5                       0                      
-system.physmem.readPktSize::6                     963                      
-system.physmem.writePktSize::0                      0                      
-system.physmem.writePktSize::1                      0                      
-system.physmem.writePktSize::2                      0                      
-system.physmem.writePktSize::3                      0                      
-system.physmem.writePktSize::4                      0                      
-system.physmem.writePktSize::5                      0                      
-system.physmem.writePktSize::6                      0                      
-system.physmem.rdQLenPdf::0                       329                      
-system.physmem.rdQLenPdf::1                       321                      
-system.physmem.rdQLenPdf::2                       178                      
-system.physmem.rdQLenPdf::3                        95                      
-system.physmem.rdQLenPdf::4                        35                      
-system.physmem.rdQLenPdf::5                         5                      
-system.physmem.rdQLenPdf::6                         0                      
-system.physmem.rdQLenPdf::7                         0                      
-system.physmem.rdQLenPdf::8                         0                      
-system.physmem.rdQLenPdf::9                         0                      
-system.physmem.rdQLenPdf::10                        0                      
-system.physmem.rdQLenPdf::11                        0                      
-system.physmem.rdQLenPdf::12                        0                      
-system.physmem.rdQLenPdf::13                        0                      
-system.physmem.rdQLenPdf::14                        0                      
-system.physmem.rdQLenPdf::15                        0                      
-system.physmem.rdQLenPdf::16                        0                      
-system.physmem.rdQLenPdf::17                        0                      
-system.physmem.rdQLenPdf::18                        0                      
-system.physmem.rdQLenPdf::19                        0                      
-system.physmem.rdQLenPdf::20                        0                      
-system.physmem.rdQLenPdf::21                        0                      
-system.physmem.rdQLenPdf::22                        0                      
-system.physmem.rdQLenPdf::23                        0                      
-system.physmem.rdQLenPdf::24                        0                      
-system.physmem.rdQLenPdf::25                        0                      
-system.physmem.rdQLenPdf::26                        0                      
-system.physmem.rdQLenPdf::27                        0                      
-system.physmem.rdQLenPdf::28                        0                      
-system.physmem.rdQLenPdf::29                        0                      
-system.physmem.rdQLenPdf::30                        0                      
-system.physmem.rdQLenPdf::31                        0                      
-system.physmem.wrQLenPdf::0                         0                      
-system.physmem.wrQLenPdf::1                         0                      
-system.physmem.wrQLenPdf::2                         0                      
-system.physmem.wrQLenPdf::3                         0                      
-system.physmem.wrQLenPdf::4                         0                      
-system.physmem.wrQLenPdf::5                         0                      
-system.physmem.wrQLenPdf::6                         0                      
-system.physmem.wrQLenPdf::7                         0                      
-system.physmem.wrQLenPdf::8                         0                      
-system.physmem.wrQLenPdf::9                         0                      
-system.physmem.wrQLenPdf::10                        0                      
-system.physmem.wrQLenPdf::11                        0                      
-system.physmem.wrQLenPdf::12                        0                      
-system.physmem.wrQLenPdf::13                        0                      
-system.physmem.wrQLenPdf::14                        0                      
-system.physmem.wrQLenPdf::15                        0                      
-system.physmem.wrQLenPdf::16                        0                      
-system.physmem.wrQLenPdf::17                        0                      
-system.physmem.wrQLenPdf::18                        0                      
-system.physmem.wrQLenPdf::19                        0                      
-system.physmem.wrQLenPdf::20                        0                      
-system.physmem.wrQLenPdf::21                        0                      
-system.physmem.wrQLenPdf::22                        0                      
-system.physmem.wrQLenPdf::23                        0                      
-system.physmem.wrQLenPdf::24                        0                      
-system.physmem.wrQLenPdf::25                        0                      
-system.physmem.wrQLenPdf::26                        0                      
-system.physmem.wrQLenPdf::27                        0                      
-system.physmem.wrQLenPdf::28                        0                      
-system.physmem.wrQLenPdf::29                        0                      
-system.physmem.wrQLenPdf::30                        0                      
-system.physmem.wrQLenPdf::31                        0                      
-system.physmem.wrQLenPdf::32                        0                      
-system.physmem.wrQLenPdf::33                        0                      
-system.physmem.wrQLenPdf::34                        0                      
-system.physmem.wrQLenPdf::35                        0                      
-system.physmem.wrQLenPdf::36                        0                      
-system.physmem.wrQLenPdf::37                        0                      
-system.physmem.wrQLenPdf::38                        0                      
-system.physmem.wrQLenPdf::39                        0                      
-system.physmem.wrQLenPdf::40                        0                      
-system.physmem.wrQLenPdf::41                        0                      
-system.physmem.wrQLenPdf::42                        0                      
-system.physmem.wrQLenPdf::43                        0                      
-system.physmem.wrQLenPdf::44                        0                      
-system.physmem.wrQLenPdf::45                        0                      
-system.physmem.wrQLenPdf::46                        0                      
-system.physmem.wrQLenPdf::47                        0                      
-system.physmem.wrQLenPdf::48                        0                      
-system.physmem.wrQLenPdf::49                        0                      
-system.physmem.wrQLenPdf::50                        0                      
-system.physmem.wrQLenPdf::51                        0                      
-system.physmem.wrQLenPdf::52                        0                      
-system.physmem.wrQLenPdf::53                        0                      
-system.physmem.wrQLenPdf::54                        0                      
-system.physmem.wrQLenPdf::55                        0                      
-system.physmem.wrQLenPdf::56                        0                      
-system.physmem.wrQLenPdf::57                        0                      
-system.physmem.wrQLenPdf::58                        0                      
-system.physmem.wrQLenPdf::59                        0                      
-system.physmem.wrQLenPdf::60                        0                      
-system.physmem.wrQLenPdf::61                        0                      
-system.physmem.wrQLenPdf::62                        0                      
-system.physmem.wrQLenPdf::63                        0                      
-system.physmem.bytesPerActivate::samples          202                      
-system.physmem.bytesPerActivate::mean      288.316832                      
-system.physmem.bytesPerActivate::gmean     177.342258                      
-system.physmem.bytesPerActivate::stdev     298.023303                      
-system.physmem.bytesPerActivate::0-127             71     35.15%     35.15%
-system.physmem.bytesPerActivate::128-255           55     27.23%     62.38%
-system.physmem.bytesPerActivate::256-383           17      8.42%     70.79%
-system.physmem.bytesPerActivate::384-511           14      6.93%     77.72%
-system.physmem.bytesPerActivate::512-639           12      5.94%     83.66%
-system.physmem.bytesPerActivate::640-767            6      2.97%     86.63%
-system.physmem.bytesPerActivate::768-895            9      4.46%     91.09%
-system.physmem.bytesPerActivate::896-1023            5      2.48%     93.56%
-system.physmem.bytesPerActivate::1024-1151           13      6.44%    100.00%
-system.physmem.bytesPerActivate::total            202                      
-system.physmem.totQLat                       16137750                      
-system.physmem.totMemAccLat                  34194000                      
-system.physmem.totBusLat                      4815000                      
-system.physmem.avgQLat                       16757.79                      
-system.physmem.avgBusLat                      5000.00                      
-system.physmem.avgMemAccLat                  35507.79                      
-system.physmem.avgRdBW                        2272.78                      
-system.physmem.avgWrBW                           0.00                      
-system.physmem.avgRdBWSys                     2272.78                      
-system.physmem.avgWrBWSys                        0.00                      
-system.physmem.peakBW                        12800.00                      
-system.physmem.busUtil                          17.76                      
-system.physmem.busUtilRead                      17.76                      
-system.physmem.busUtilWrite                      0.00                      
-system.physmem.avgRdQLen                         2.46                      
-system.physmem.avgWrQLen                         0.00                      
-system.physmem.readRowHits                        750                      
-system.physmem.writeRowHits                         0                      
-system.physmem.readRowHitRate                   77.88                      
-system.physmem.writeRowHitRate                    nan                      
-system.physmem.avgGap                        28127.21                      
-system.physmem.pageHitRate                      77.88                      
-system.physmem_0.actEnergy                     835380                      
-system.physmem_0.preEnergy                     428835                      
-system.physmem_0.readEnergy                   4162620                      
-system.physmem_0.writeEnergy                        0                      
-system.physmem_0.refreshEnergy           1843920.000000                      
-system.physmem_0.actBackEnergy                5930850                      
-system.physmem_0.preBackEnergy                  47520                      
-system.physmem_0.actPowerDownEnergy           6376590                      
-system.physmem_0.prePowerDownEnergy              1440                      
-system.physmem_0.selfRefreshEnergy                  0                      
-system.physmem_0.totalEnergy                 19627155                      
-system.physmem_0.averagePower              723.781875                      
-system.physmem_0.totalIdleTime               13833750                      
-system.physmem_0.memoryStateTime::IDLE          40500                      
-system.physmem_0.memoryStateTime::REF          780000                      
-system.physmem_0.memoryStateTime::SREF              0                      
-system.physmem_0.memoryStateTime::PRE_PDN         3750                      
-system.physmem_0.memoryStateTime::ACT        12310750                      
-system.physmem_0.memoryStateTime::ACT_PDN     13982500                      
-system.physmem_1.actEnergy                     685440                      
-system.physmem_1.preEnergy                     337755                      
-system.physmem_1.readEnergy                   2713200                      
-system.physmem_1.writeEnergy                        0                      
-system.physmem_1.refreshEnergy           1843920.000000                      
-system.physmem_1.actBackEnergy                4668300                      
-system.physmem_1.preBackEnergy                 160320                      
-system.physmem_1.actPowerDownEnergy           7500060                      
-system.physmem_1.prePowerDownEnergy              5760                      
-system.physmem_1.selfRefreshEnergy                  0                      
-system.physmem_1.totalEnergy                 17914755                      
-system.physmem_1.averagePower              660.634461                      
-system.physmem_1.totalIdleTime               16457500                      
-system.physmem_1.memoryStateTime::IDLE         306000                      
-system.physmem_1.memoryStateTime::REF          780000                      
-system.physmem_1.memoryStateTime::SREF              0                      
-system.physmem_1.memoryStateTime::PRE_PDN        15250                      
-system.physmem_1.memoryStateTime::ACT         9574000                      
-system.physmem_1.memoryStateTime::ACT_PDN     16442250                      
-system.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.branchPred.lookups                    5015                      
-system.cpu.branchPred.condPredicted              3001                      
-system.cpu.branchPred.condIncorrect               806                      
-system.cpu.branchPred.BTBLookups                 3809                      
-system.cpu.branchPred.BTBHits                    1166                      
-system.cpu.branchPred.BTBCorrect                    0                      
-system.cpu.branchPred.BTBHitPct             30.611709                      
-system.cpu.branchPred.usedRAS                     698                      
-system.cpu.branchPred.RASInCorrect                 53                      
-system.cpu.branchPred.indirectLookups             824                      
-system.cpu.branchPred.indirectHits                156                      
-system.cpu.branchPred.indirectMisses              668                      
-system.cpu.branchPredindirectMispredicted          131                      
-system.cpu_clk_domain.clock                       500                      
-system.cpu.dtb.fetch_hits                           0                      
-system.cpu.dtb.fetch_misses                         0                      
-system.cpu.dtb.fetch_acv                            0                      
-system.cpu.dtb.fetch_accesses                       0                      
-system.cpu.dtb.read_hits                         4101                      
-system.cpu.dtb.read_misses                         90                      
-system.cpu.dtb.read_acv                             0                      
-system.cpu.dtb.read_accesses                     4191                      
-system.cpu.dtb.write_hits                        1999                      
-system.cpu.dtb.write_misses                        49                      
-system.cpu.dtb.write_acv                            0                      
-system.cpu.dtb.write_accesses                    2048                      
-system.cpu.dtb.data_hits                         6100                      
-system.cpu.dtb.data_misses                        139                      
-system.cpu.dtb.data_acv                             0                      
-system.cpu.dtb.data_accesses                     6239                      
-system.cpu.itb.fetch_hits                        3896                      
-system.cpu.itb.fetch_misses                        51                      
-system.cpu.itb.fetch_acv                            0                      
-system.cpu.itb.fetch_accesses                    3947                      
-system.cpu.itb.read_hits                            0                      
-system.cpu.itb.read_misses                          0                      
-system.cpu.itb.read_acv                             0                      
-system.cpu.itb.read_accesses                        0                      
-system.cpu.itb.write_hits                           0                      
-system.cpu.itb.write_misses                         0                      
-system.cpu.itb.write_acv                            0                      
-system.cpu.itb.write_accesses                       0                      
-system.cpu.itb.data_hits                            0                      
-system.cpu.itb.data_misses                          0                      
-system.cpu.itb.data_acv                             0                      
-system.cpu.itb.data_accesses                        0                      
-system.cpu.workload0.numSyscalls                   17                      
-system.cpu.workload1.numSyscalls                   17                      
-system.cpu.pwrStateResidencyTicks::ON        27117500                      
-system.cpu.numCycles                            54236                      
-system.cpu.numWorkItemsStarted                      0                      
-system.cpu.numWorkItemsCompleted                    0                      
-system.cpu.fetch.icacheStallCycles                769                      
-system.cpu.fetch.Insts                          28725                      
-system.cpu.fetch.Branches                        5015                      
-system.cpu.fetch.predictedBranches               2020                      
-system.cpu.fetch.Cycles                          9652                      
-system.cpu.fetch.SquashCycles                     886                      
-system.cpu.fetch.MiscStallCycles                  340                      
-system.cpu.fetch.CacheLines                      3896                      
-system.cpu.fetch.IcacheSquashes                   581                      
-system.cpu.fetch.rateDist::samples              26268                      
-system.cpu.fetch.rateDist::mean              1.093536                      
-system.cpu.fetch.rateDist::stdev             2.491751                      
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00%
-system.cpu.fetch.rateDist::0                    21148     80.51%     80.51%
-system.cpu.fetch.rateDist::1                      495      1.88%     82.39%
-system.cpu.fetch.rateDist::2                      401      1.53%     83.92%
-system.cpu.fetch.rateDist::3                      445      1.69%     85.61%
-system.cpu.fetch.rateDist::4                      462      1.76%     87.37%
-system.cpu.fetch.rateDist::5                      360      1.37%     88.74%
-system.cpu.fetch.rateDist::6                      460      1.75%     90.49%
-system.cpu.fetch.rateDist::7                      291      1.11%     91.60%
-system.cpu.fetch.rateDist::8                     2206      8.40%    100.00%
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00%
-system.cpu.fetch.rateDist::min_value                0                      
-system.cpu.fetch.rateDist::max_value                8                      
-system.cpu.fetch.rateDist::total                26268                      
-system.cpu.fetch.branchRate                  0.092466                      
-system.cpu.fetch.rate                        0.529630                      
-system.cpu.decode.IdleCycles                    36232                      
-system.cpu.decode.BlockedCycles                 10559                      
-system.cpu.decode.RunCycles                      4004                      
-system.cpu.decode.UnblockCycles                   499                      
-system.cpu.decode.SquashCycles                    740                      
-system.cpu.decode.BranchResolved                 1233                      
-system.cpu.decode.BranchMispred                   150                      
-system.cpu.decode.DecodedInsts                  24986                      
-system.cpu.decode.SquashedInsts                   353                      
-system.cpu.rename.SquashCycles                    740                      
-system.cpu.rename.IdleCycles                    36582                      
-system.cpu.rename.BlockCycles                    3853                      
-system.cpu.rename.serializeStallCycles           1413                      
-system.cpu.rename.RunCycles                      4167                      
-system.cpu.rename.UnblockCycles                  5279                      
-system.cpu.rename.RenamedInsts                  23947                      
-system.cpu.rename.ROBFullEvents                    27                      
-system.cpu.rename.IQFullEvents                    237                      
-system.cpu.rename.LQFullEvents                    333                      
-system.cpu.rename.SQFullEvents                   4524                      
-system.cpu.rename.RenamedOperands               17933                      
-system.cpu.rename.RenameLookups                 29997                      
-system.cpu.rename.int_rename_lookups            29979                      
-system.cpu.rename.fp_rename_lookups                16                      
-system.cpu.rename.CommittedMaps                  9154                      
-system.cpu.rename.UndoneMaps                     8779                      
-system.cpu.rename.serializingInsts                 57                      
-system.cpu.rename.tempSerializingInsts             45                      
-system.cpu.rename.skidInsts                      1716                      
-system.cpu.memDep0.insertedLoads                 1914                      
-system.cpu.memDep0.insertedStores                1068                      
-system.cpu.memDep0.conflictingLoads                 6                      
-system.cpu.memDep0.conflictingStores                0                      
-system.cpu.memDep1.insertedLoads                 2644                      
-system.cpu.memDep1.insertedStores                1299                      
-system.cpu.memDep1.conflictingLoads                14                      
-system.cpu.memDep1.conflictingStores                4                      
-system.cpu.iq.iqInstsAdded                      22142                      
-system.cpu.iq.iqNonSpecInstsAdded                  52                      
-system.cpu.iq.iqInstsIssued                     19454                      
-system.cpu.iq.iqSquashedInstsIssued                57                      
-system.cpu.iq.iqSquashedInstsExamined            9423                      
-system.cpu.iq.iqSquashedOperandsExamined         4923                      
-system.cpu.iq.iqSquashedNonSpecRemoved             18                      
-system.cpu.iq.issued_per_cycle::samples         26268                      
-system.cpu.iq.issued_per_cycle::mean         0.740597                      
-system.cpu.iq.issued_per_cycle::stdev        1.454117                      
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00%
-system.cpu.iq.issued_per_cycle::0               18898     71.94%     71.94%
-system.cpu.iq.issued_per_cycle::1                2350      8.95%     80.89%
-system.cpu.iq.issued_per_cycle::2                1639      6.24%     87.13%
-system.cpu.iq.issued_per_cycle::3                1288      4.90%     92.03%
-system.cpu.iq.issued_per_cycle::4                1107      4.21%     96.25%
-system.cpu.iq.issued_per_cycle::5                 560      2.13%     98.38%
-system.cpu.iq.issued_per_cycle::6                 292      1.11%     99.49%
-system.cpu.iq.issued_per_cycle::7                  90      0.34%     99.83%
-system.cpu.iq.issued_per_cycle::8                  44      0.17%    100.00%
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00%
-system.cpu.iq.issued_per_cycle::min_value            0                      
-system.cpu.iq.issued_per_cycle::max_value            8                      
-system.cpu.iq.issued_per_cycle::total           26268                      
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00%
-system.cpu.iq.fu_full::IntAlu                      27      9.18%      9.18%
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.18%
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatMisc                    0      0.00%      9.18%
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.18%
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.18%
-system.cpu.iq.fu_full::MemRead                    190     64.63%     73.81%
-system.cpu.iq.fu_full::MemWrite                    74     25.17%     98.98%
-system.cpu.iq.fu_full::FloatMemRead                 0      0.00%     98.98%
-system.cpu.iq.fu_full::FloatMemWrite                3      1.02%    100.00%
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00%
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00%
-system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02%
-system.cpu.iq.FU_type_0::IntAlu                  5807     66.00%     66.02%
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.03%
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.03%
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.05%
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     66.05%
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.05%
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.05%
-system.cpu.iq.FU_type_0::MemRead                 1993     22.65%     88.70%
-system.cpu.iq.FU_type_0::MemWrite                 986     11.21%     99.91%
-system.cpu.iq.FU_type_0::FloatMemRead               1      0.01%     99.92%
-system.cpu.iq.FU_type_0::FloatMemWrite              7      0.08%    100.00%
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00%
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00%
-system.cpu.iq.FU_type_0::total                   8799                      
-system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02%
-system.cpu.iq.FU_type_1::IntAlu                  7099     66.63%     66.64%
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.65%
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.65%
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.67%
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatMultAcc               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatMisc                  0      0.00%     66.67%
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.67%
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.67%
-system.cpu.iq.FU_type_1::MemRead                 2427     22.78%     89.45%
-system.cpu.iq.FU_type_1::MemWrite                1116     10.47%     99.92%
-system.cpu.iq.FU_type_1::FloatMemRead               1      0.01%     99.93%
-system.cpu.iq.FU_type_1::FloatMemWrite              7      0.07%    100.00%
-system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00%
-system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00%
-system.cpu.iq.FU_type_1::total                  10655                      
-system.cpu.iq.FU_type::total                    19454      0.00%      0.00%
-system.cpu.iq.rate                           0.358692                      
-system.cpu.iq.fu_busy_cnt::0                      148                      
-system.cpu.iq.fu_busy_cnt::1                      146                      
-system.cpu.iq.fu_busy_cnt::total                  294                      
-system.cpu.iq.fu_busy_rate::0                0.007608                      
-system.cpu.iq.fu_busy_rate::1                0.007505                      
-system.cpu.iq.fu_busy_rate::total            0.015113                      
-system.cpu.iq.int_inst_queue_reads              65484                      
-system.cpu.iq.int_inst_queue_writes             31629                      
-system.cpu.iq.int_inst_queue_wakeup_accesses        17691                      
-system.cpu.iq.fp_inst_queue_reads                  43                      
-system.cpu.iq.fp_inst_queue_writes                 20                      
-system.cpu.iq.fp_inst_queue_wakeup_accesses           20                      
-system.cpu.iq.int_alu_accesses                  19721                      
-system.cpu.iq.fp_alu_accesses                      23                      
-system.cpu.iew.lsq.thread0.forwLoads               41                      
-system.cpu.iew.lsq.thread0.invAddrLoads             0                      
-system.cpu.iew.lsq.thread0.squashedLoads          729                      
-system.cpu.iew.lsq.thread0.ignoredResponses            0                      
-system.cpu.iew.lsq.thread0.memOrderViolation           12                      
-system.cpu.iew.lsq.thread0.squashedStores          203                      
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                      
-system.cpu.iew.lsq.thread0.blockedLoads             0                      
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                      
-system.cpu.iew.lsq.thread0.cacheBlocked           273                      
-system.cpu.iew.lsq.thread1.forwLoads               90                      
-system.cpu.iew.lsq.thread1.invAddrLoads             0                      
-system.cpu.iew.lsq.thread1.squashedLoads         1459                      
-system.cpu.iew.lsq.thread1.ignoredResponses            9                      
-system.cpu.iew.lsq.thread1.memOrderViolation           21                      
-system.cpu.iew.lsq.thread1.squashedStores          434                      
-system.cpu.iew.lsq.thread1.invAddrSwpfs             0                      
-system.cpu.iew.lsq.thread1.blockedLoads             0                      
-system.cpu.iew.lsq.thread1.rescheduledLoads            1                      
-system.cpu.iew.lsq.thread1.cacheBlocked           221                      
-system.cpu.iew.iewIdleCycles                        0                      
-system.cpu.iew.iewSquashCycles                    740                      
-system.cpu.iew.iewBlockCycles                    2317                      
-system.cpu.iew.iewUnblockCycles                   426                      
-system.cpu.iew.iewDispatchedInsts               22329                      
-system.cpu.iew.iewDispSquashedInsts               159                      
-system.cpu.iew.iewDispLoadInsts                  4558                      
-system.cpu.iew.iewDispStoreInsts                 2367                      
-system.cpu.iew.iewDispNonSpecInsts                 52                      
-system.cpu.iew.iewIQFullEvents                     21                      
-system.cpu.iew.iewLSQFullEvents                   403                      
-system.cpu.iew.memOrderViolationEvents             33                      
-system.cpu.iew.predictedTakenIncorrect            142                      
-system.cpu.iew.predictedNotTakenIncorrect          645                      
-system.cpu.iew.branchMispredicts                  787                      
-system.cpu.iew.iewExecutedInsts                 18732                      
-system.cpu.iew.iewExecLoadInsts::0               1919                      
-system.cpu.iew.iewExecLoadInsts::1               2279                      
-system.cpu.iew.iewExecLoadInsts::total           4198                      
-system.cpu.iew.iewExecSquashedInsts               722                      
-system.cpu.iew.exec_swp::0                          0                      
-system.cpu.iew.exec_swp::1                          0                      
-system.cpu.iew.exec_swp::total                      0                      
-system.cpu.iew.exec_nop::0                         63                      
-system.cpu.iew.exec_nop::1                         72                      
-system.cpu.iew.exec_nop::total                    135                      
-system.cpu.iew.exec_refs::0                      2905                      
-system.cpu.iew.exec_refs::1                      3353                      
-system.cpu.iew.exec_refs::total                  6258                      
-system.cpu.iew.exec_branches::0                  1375                      
-system.cpu.iew.exec_branches::1                  1612                      
-system.cpu.iew.exec_branches::total              2987                      
-system.cpu.iew.exec_stores::0                     986                      
-system.cpu.iew.exec_stores::1                    1074                      
-system.cpu.iew.exec_stores::total                2060                      
-system.cpu.iew.exec_rate                     0.345379                      
-system.cpu.iew.wb_sent::0                        8229                      
-system.cpu.iew.wb_sent::1                        9751                      
-system.cpu.iew.wb_sent::total                   17980                      
-system.cpu.iew.wb_count::0                       8135                      
-system.cpu.iew.wb_count::1                       9576                      
-system.cpu.iew.wb_count::total                  17711                      
-system.cpu.iew.wb_producers::0                   4316                      
-system.cpu.iew.wb_producers::1                   5060                      
-system.cpu.iew.wb_producers::total               9376                      
-system.cpu.iew.wb_consumers::0                   5785                      
-system.cpu.iew.wb_consumers::1                   6812                      
-system.cpu.iew.wb_consumers::total              12597                      
-system.cpu.iew.wb_rate::0                    0.149993                      
-system.cpu.iew.wb_rate::1                    0.176562                      
-system.cpu.iew.wb_rate::total                0.326554                      
-system.cpu.iew.wb_fanout::0                  0.746067                      
-system.cpu.iew.wb_fanout::1                  0.742807                      
-system.cpu.iew.wb_fanout::total              0.744304                      
-system.cpu.commit.commitSquashedInsts            9512                      
-system.cpu.commit.commitNonSpecStalls              34                      
-system.cpu.commit.branchMispredicts               661                      
-system.cpu.commit.committed_per_cycle::samples        26245                      
-system.cpu.commit.committed_per_cycle::mean     0.487864                      
-system.cpu.commit.committed_per_cycle::stdev     1.400805                      
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00%
-system.cpu.commit.committed_per_cycle::0        21282     81.09%     81.09%
-system.cpu.commit.committed_per_cycle::1         2428      9.25%     90.34%
-system.cpu.commit.committed_per_cycle::2          980      3.73%     94.08%
-system.cpu.commit.committed_per_cycle::3          381      1.45%     95.53%
-system.cpu.commit.committed_per_cycle::4          266      1.01%     96.54%
-system.cpu.commit.committed_per_cycle::5          163      0.62%     97.16%
-system.cpu.commit.committed_per_cycle::6          223      0.85%     98.01%
-system.cpu.commit.committed_per_cycle::7          120      0.46%     98.47%
-system.cpu.commit.committed_per_cycle::8          402      1.53%    100.00%
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00%
-system.cpu.commit.committed_per_cycle::min_value            0                      
-system.cpu.commit.committed_per_cycle::max_value            8                      
-system.cpu.commit.committed_per_cycle::total        26245                      
-system.cpu.commit.committedInsts::0              6402                      
-system.cpu.commit.committedInsts::1              6402                      
-system.cpu.commit.committedInsts::total         12804                      
-system.cpu.commit.committedOps::0                6402                      
-system.cpu.commit.committedOps::1                6402                      
-system.cpu.commit.committedOps::total           12804                      
-system.cpu.commit.swp_count::0                      0                      
-system.cpu.commit.swp_count::1                      0                      
-system.cpu.commit.swp_count::total                  0                      
-system.cpu.commit.refs::0                        2050                      
-system.cpu.commit.refs::1                        2050                      
-system.cpu.commit.refs::total                    4100                      
-system.cpu.commit.loads::0                       1185                      
-system.cpu.commit.loads::1                       1185                      
-system.cpu.commit.loads::total                   2370                      
-system.cpu.commit.membars::0                        0                      
-system.cpu.commit.membars::1                        0                      
-system.cpu.commit.membars::total                    0                      
-system.cpu.commit.branches::0                    1056                      
-system.cpu.commit.branches::1                    1056                      
-system.cpu.commit.branches::total                2112                      
-system.cpu.commit.fp_insts::0                      10                      
-system.cpu.commit.fp_insts::1                      10                      
-system.cpu.commit.fp_insts::total                  20                      
-system.cpu.commit.int_insts::0                   6319                      
-system.cpu.commit.int_insts::1                   6319                      
-system.cpu.commit.int_insts::total              12638                      
-system.cpu.commit.function_calls::0               127                      
-system.cpu.commit.function_calls::1               127                      
-system.cpu.commit.function_calls::total           254                      
-system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30%
-system.cpu.commit.op_class_0::IntAlu             4330     67.64%     67.93%
-system.cpu.commit.op_class_0::IntMult               1      0.02%     67.95%
-system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.95%
-system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.98%
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatMisc             0      0.00%     67.98%
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.98%
-system.cpu.commit.op_class_0::MemRead            1184     18.49%     86.47%
-system.cpu.commit.op_class_0::MemWrite            858     13.40%     99.88%
-system.cpu.commit.op_class_0::FloatMemRead            1      0.02%     99.89%
-system.cpu.commit.op_class_0::FloatMemWrite            7      0.11%    100.00%
-system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00%
-system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00%
-system.cpu.commit.op_class_0::total              6402                      
-system.cpu.commit.op_class_1::No_OpClass           19      0.30%      0.30%
-system.cpu.commit.op_class_1::IntAlu             4330     67.64%     67.93%
-system.cpu.commit.op_class_1::IntMult               1      0.02%     67.95%
-system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.95%
-system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.98%
-system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatMisc             0      0.00%     67.98%
-system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.98%
-system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.98%
-system.cpu.commit.op_class_1::MemRead            1184     18.49%     86.47%
-system.cpu.commit.op_class_1::MemWrite            858     13.40%     99.88%
-system.cpu.commit.op_class_1::FloatMemRead            1      0.02%     99.89%
-system.cpu.commit.op_class_1::FloatMemWrite            7      0.11%    100.00%
-system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00%
-system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00%
-system.cpu.commit.op_class_1::total              6402                      
-system.cpu.commit.op_class::total               12804      0.00%      0.00%
-system.cpu.commit.bw_lim_events                   402                      
-system.cpu.rob.rob_reads                       114640                      
-system.cpu.rob.rob_writes                       46397                      
-system.cpu.timesIdled                             397                      
-system.cpu.idleCycles                           27968                      
-system.cpu.committedInsts::0                     6385                      
-system.cpu.committedInsts::1                     6385                      
-system.cpu.committedInsts::total                12770                      
-system.cpu.committedOps::0                       6385                      
-system.cpu.committedOps::1                       6385                      
-system.cpu.committedOps::total                  12770                      
-system.cpu.cpi::0                            8.494283                      
-system.cpu.cpi::1                            8.494283                      
-system.cpu.cpi_total                         4.247142                      
-system.cpu.ipc::0                            0.117726                      
-system.cpu.ipc::1                            0.117726                      
-system.cpu.ipc_total                         0.235452                      
-system.cpu.int_regfile_reads                    23899                      
-system.cpu.int_regfile_writes                   13306                      
-system.cpu.fp_regfile_reads                        16                      
-system.cpu.fp_regfile_writes                        4                      
-system.cpu.misc_regfile_reads                       2                      
-system.cpu.misc_regfile_writes                      2                      
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.dcache.tags.replacements::0              0                      
-system.cpu.dcache.tags.replacements::1              0                      
-system.cpu.dcache.tags.replacements::total            0                      
-system.cpu.dcache.tags.tagsinuse           217.668632                      
-system.cpu.dcache.tags.total_refs                4250                      
-system.cpu.dcache.tags.sampled_refs               342                      
-system.cpu.dcache.tags.avg_refs             12.426901                      
-system.cpu.dcache.tags.warmup_cycle                 0                      
-system.cpu.dcache.tags.occ_blocks::cpu.data   217.668632                      
-system.cpu.dcache.tags.occ_percent::cpu.data     0.053142                      
-system.cpu.dcache.tags.occ_percent::total     0.053142                      
-system.cpu.dcache.tags.occ_task_id_blocks::1024          342                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                      
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                      
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.083496                      
-system.cpu.dcache.tags.tag_accesses             10882                      
-system.cpu.dcache.tags.data_accesses            10882                      
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.dcache.ReadReq_hits::cpu.data         3235                      
-system.cpu.dcache.ReadReq_hits::total            3235                      
-system.cpu.dcache.WriteReq_hits::cpu.data         1015                      
-system.cpu.dcache.WriteReq_hits::total           1015                      
-system.cpu.dcache.demand_hits::cpu.data          4250                      
-system.cpu.dcache.demand_hits::total             4250                      
-system.cpu.dcache.overall_hits::cpu.data         4250                      
-system.cpu.dcache.overall_hits::total            4250                      
-system.cpu.dcache.ReadReq_misses::cpu.data          305                      
-system.cpu.dcache.ReadReq_misses::total           305                      
-system.cpu.dcache.WriteReq_misses::cpu.data          715                      
-system.cpu.dcache.WriteReq_misses::total          715                      
-system.cpu.dcache.demand_misses::cpu.data         1020                      
-system.cpu.dcache.demand_misses::total           1020                      
-system.cpu.dcache.overall_misses::cpu.data         1020                      
-system.cpu.dcache.overall_misses::total          1020                      
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24356500                      
-system.cpu.dcache.ReadReq_miss_latency::total     24356500                      
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     50960445                      
-system.cpu.dcache.WriteReq_miss_latency::total     50960445                      
-system.cpu.dcache.demand_miss_latency::cpu.data     75316945                      
-system.cpu.dcache.demand_miss_latency::total     75316945                      
-system.cpu.dcache.overall_miss_latency::cpu.data     75316945                      
-system.cpu.dcache.overall_miss_latency::total     75316945                      
-system.cpu.dcache.ReadReq_accesses::cpu.data         3540                      
-system.cpu.dcache.ReadReq_accesses::total         3540                      
-system.cpu.dcache.WriteReq_accesses::cpu.data         1730                      
-system.cpu.dcache.WriteReq_accesses::total         1730                      
-system.cpu.dcache.demand_accesses::cpu.data         5270                      
-system.cpu.dcache.demand_accesses::total         5270                      
-system.cpu.dcache.overall_accesses::cpu.data         5270                      
-system.cpu.dcache.overall_accesses::total         5270                      
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086158                      
-system.cpu.dcache.ReadReq_miss_rate::total     0.086158                      
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.413295                      
-system.cpu.dcache.WriteReq_miss_rate::total     0.413295                      
-system.cpu.dcache.demand_miss_rate::cpu.data     0.193548                      
-system.cpu.dcache.demand_miss_rate::total     0.193548                      
-system.cpu.dcache.overall_miss_rate::cpu.data     0.193548                      
-system.cpu.dcache.overall_miss_rate::total     0.193548                      
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79857.377049                      
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79857.377049                      
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71273.349650                      
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71273.349650                      
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73840.142157                      
-system.cpu.dcache.demand_avg_miss_latency::total 73840.142157                      
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73840.142157                      
-system.cpu.dcache.overall_avg_miss_latency::total 73840.142157                      
-system.cpu.dcache.blocked_cycles::no_mshrs         5867                      
-system.cpu.dcache.blocked_cycles::no_targets            0                      
-system.cpu.dcache.blocked::no_mshrs               115                      
-system.cpu.dcache.blocked::no_targets               0                      
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    51.017391                      
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          107                      
-system.cpu.dcache.ReadReq_mshr_hits::total          107                      
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          570                      
-system.cpu.dcache.WriteReq_mshr_hits::total          570                      
-system.cpu.dcache.demand_mshr_hits::cpu.data          677                      
-system.cpu.dcache.demand_mshr_hits::total          677                      
-system.cpu.dcache.overall_mshr_hits::cpu.data          677                      
-system.cpu.dcache.overall_mshr_hits::total          677                      
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          198                      
-system.cpu.dcache.ReadReq_mshr_misses::total          198                      
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                      
-system.cpu.dcache.WriteReq_mshr_misses::total          145                      
-system.cpu.dcache.demand_mshr_misses::cpu.data          343                      
-system.cpu.dcache.demand_mshr_misses::total          343                      
-system.cpu.dcache.overall_mshr_misses::cpu.data          343                      
-system.cpu.dcache.overall_mshr_misses::total          343                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18395500                      
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     18395500                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12405489                      
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     12405489                      
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30800989                      
-system.cpu.dcache.demand_mshr_miss_latency::total     30800989                      
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30800989                      
-system.cpu.dcache.overall_mshr_miss_latency::total     30800989                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.055932                      
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055932                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                      
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                      
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.065085                      
-system.cpu.dcache.demand_mshr_miss_rate::total     0.065085                      
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.065085                      
-system.cpu.dcache.overall_mshr_miss_rate::total     0.065085                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92906.565657                      
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92906.565657                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85555.096552                      
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85555.096552                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89798.801749                      
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 89798.801749                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89798.801749                      
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 89798.801749                      
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.icache.tags.replacements::0              7                      
-system.cpu.icache.tags.replacements::1              0                      
-system.cpu.icache.tags.replacements::total            7                      
-system.cpu.icache.tags.tagsinuse           317.013453                      
-system.cpu.icache.tags.total_refs                2987                      
-system.cpu.icache.tags.sampled_refs               623                      
-system.cpu.icache.tags.avg_refs              4.794543                      
-system.cpu.icache.tags.warmup_cycle                 0                      
-system.cpu.icache.tags.occ_blocks::cpu.inst   317.013453                      
-system.cpu.icache.tags.occ_percent::cpu.inst     0.154792                      
-system.cpu.icache.tags.occ_percent::total     0.154792                      
-system.cpu.icache.tags.occ_task_id_blocks::1024          616                      
-system.cpu.icache.tags.age_task_id_blocks_1024::0          227                      
-system.cpu.icache.tags.age_task_id_blocks_1024::1          389                      
-system.cpu.icache.tags.occ_task_id_percent::1024     0.300781                      
-system.cpu.icache.tags.tag_accesses              8411                      
-system.cpu.icache.tags.data_accesses             8411                      
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.icache.ReadReq_hits::cpu.inst         2987                      
-system.cpu.icache.ReadReq_hits::total            2987                      
-system.cpu.icache.demand_hits::cpu.inst          2987                      
-system.cpu.icache.demand_hits::total             2987                      
-system.cpu.icache.overall_hits::cpu.inst         2987                      
-system.cpu.icache.overall_hits::total            2987                      
-system.cpu.icache.ReadReq_misses::cpu.inst          907                      
-system.cpu.icache.ReadReq_misses::total           907                      
-system.cpu.icache.demand_misses::cpu.inst          907                      
-system.cpu.icache.demand_misses::total            907                      
-system.cpu.icache.overall_misses::cpu.inst          907                      
-system.cpu.icache.overall_misses::total           907                      
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     73557995                      
-system.cpu.icache.ReadReq_miss_latency::total     73557995                      
-system.cpu.icache.demand_miss_latency::cpu.inst     73557995                      
-system.cpu.icache.demand_miss_latency::total     73557995                      
-system.cpu.icache.overall_miss_latency::cpu.inst     73557995                      
-system.cpu.icache.overall_miss_latency::total     73557995                      
-system.cpu.icache.ReadReq_accesses::cpu.inst         3894                      
-system.cpu.icache.ReadReq_accesses::total         3894                      
-system.cpu.icache.demand_accesses::cpu.inst         3894                      
-system.cpu.icache.demand_accesses::total         3894                      
-system.cpu.icache.overall_accesses::cpu.inst         3894                      
-system.cpu.icache.overall_accesses::total         3894                      
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.232922                      
-system.cpu.icache.ReadReq_miss_rate::total     0.232922                      
-system.cpu.icache.demand_miss_rate::cpu.inst     0.232922                      
-system.cpu.icache.demand_miss_rate::total     0.232922                      
-system.cpu.icache.overall_miss_rate::cpu.inst     0.232922                      
-system.cpu.icache.overall_miss_rate::total     0.232922                      
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81100.325248                      
-system.cpu.icache.ReadReq_avg_miss_latency::total 81100.325248                      
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 81100.325248                      
-system.cpu.icache.demand_avg_miss_latency::total 81100.325248                      
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 81100.325248                      
-system.cpu.icache.overall_avg_miss_latency::total 81100.325248                      
-system.cpu.icache.blocked_cycles::no_mshrs         3028                      
-system.cpu.icache.blocked_cycles::no_targets            0                      
-system.cpu.icache.blocked::no_mshrs                53                      
-system.cpu.icache.blocked::no_targets               0                      
-system.cpu.icache.avg_blocked_cycles::no_mshrs    57.132075                      
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.icache.writebacks::writebacks            7                      
-system.cpu.icache.writebacks::total                 7                      
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          284                      
-system.cpu.icache.ReadReq_mshr_hits::total          284                      
-system.cpu.icache.demand_mshr_hits::cpu.inst          284                      
-system.cpu.icache.demand_mshr_hits::total          284                      
-system.cpu.icache.overall_mshr_hits::cpu.inst          284                      
-system.cpu.icache.overall_mshr_hits::total          284                      
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          623                      
-system.cpu.icache.ReadReq_mshr_misses::total          623                      
-system.cpu.icache.demand_mshr_misses::cpu.inst          623                      
-system.cpu.icache.demand_mshr_misses::total          623                      
-system.cpu.icache.overall_mshr_misses::cpu.inst          623                      
-system.cpu.icache.overall_mshr_misses::total          623                      
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     54126496                      
-system.cpu.icache.ReadReq_mshr_miss_latency::total     54126496                      
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     54126496                      
-system.cpu.icache.demand_mshr_miss_latency::total     54126496                      
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     54126496                      
-system.cpu.icache.overall_mshr_miss_latency::total     54126496                      
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.159990                      
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.159990                      
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.159990                      
-system.cpu.icache.demand_mshr_miss_rate::total     0.159990                      
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.159990                      
-system.cpu.icache.overall_mshr_miss_rate::total     0.159990                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86880.410915                      
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86880.410915                      
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86880.410915                      
-system.cpu.icache.demand_avg_mshr_miss_latency::total 86880.410915                      
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86880.410915                      
-system.cpu.icache.overall_avg_mshr_miss_latency::total 86880.410915                      
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.l2cache.tags.replacements::0             0                      
-system.cpu.l2cache.tags.replacements::1             0                      
-system.cpu.l2cache.tags.replacements::total            0                      
-system.cpu.l2cache.tags.tagsinuse          535.282693                      
-system.cpu.l2cache.tags.total_refs                 10                      
-system.cpu.l2cache.tags.sampled_refs              962                      
-system.cpu.l2cache.tags.avg_refs             0.010395                      
-system.cpu.l2cache.tags.warmup_cycle                0                      
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   317.481637                      
-system.cpu.l2cache.tags.occ_blocks::cpu.data   217.801056                      
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009689                      
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.006647                      
-system.cpu.l2cache.tags.occ_percent::total     0.016336                      
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          962                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          291                      
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          671                      
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.029358                      
-system.cpu.l2cache.tags.tag_accesses             8746                      
-system.cpu.l2cache.tags.data_accesses            8746                      
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.l2cache.WritebackClean_hits::writebacks            7                      
-system.cpu.l2cache.WritebackClean_hits::total            7                      
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                      
-system.cpu.l2cache.ReadCleanReq_hits::total            3                      
-system.cpu.l2cache.demand_hits::cpu.inst            3                      
-system.cpu.l2cache.demand_hits::total               3                      
-system.cpu.l2cache.overall_hits::cpu.inst            3                      
-system.cpu.l2cache.overall_hits::total              3                      
-system.cpu.l2cache.ReadExReq_misses::cpu.data          146                      
-system.cpu.l2cache.ReadExReq_misses::total          146                      
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          620                      
-system.cpu.l2cache.ReadCleanReq_misses::total          620                      
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          197                      
-system.cpu.l2cache.ReadSharedReq_misses::total          197                      
-system.cpu.l2cache.demand_misses::cpu.inst          620                      
-system.cpu.l2cache.demand_misses::cpu.data          343                      
-system.cpu.l2cache.demand_misses::total           963                      
-system.cpu.l2cache.overall_misses::cpu.inst          620                      
-system.cpu.l2cache.overall_misses::cpu.data          343                      
-system.cpu.l2cache.overall_misses::total          963                      
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12255000                      
-system.cpu.l2cache.ReadExReq_miss_latency::total     12255000                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     53153500                      
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     53153500                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     18016500                      
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     18016500                      
-system.cpu.l2cache.demand_miss_latency::cpu.inst     53153500                      
-system.cpu.l2cache.demand_miss_latency::cpu.data     30271500                      
-system.cpu.l2cache.demand_miss_latency::total     83425000                      
-system.cpu.l2cache.overall_miss_latency::cpu.inst     53153500                      
-system.cpu.l2cache.overall_miss_latency::cpu.data     30271500                      
-system.cpu.l2cache.overall_miss_latency::total     83425000                      
-system.cpu.l2cache.WritebackClean_accesses::writebacks            7                      
-system.cpu.l2cache.WritebackClean_accesses::total            7                      
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                      
-system.cpu.l2cache.ReadExReq_accesses::total          146                      
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          623                      
-system.cpu.l2cache.ReadCleanReq_accesses::total          623                      
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          197                      
-system.cpu.l2cache.ReadSharedReq_accesses::total          197                      
-system.cpu.l2cache.demand_accesses::cpu.inst          623                      
-system.cpu.l2cache.demand_accesses::cpu.data          343                      
-system.cpu.l2cache.demand_accesses::total          966                      
-system.cpu.l2cache.overall_accesses::cpu.inst          623                      
-system.cpu.l2cache.overall_accesses::cpu.data          343                      
-system.cpu.l2cache.overall_accesses::total          966                      
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                      
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.995185                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                      
-system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                      
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                      
-system.cpu.l2cache.demand_miss_rate::total     0.996894                      
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                      
-system.cpu.l2cache.overall_miss_rate::total     0.996894                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83938.356164                      
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83938.356164                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85731.451613                      
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85731.451613                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91454.314721                      
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91454.314721                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85731.451613                      
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88255.102041                      
-system.cpu.l2cache.demand_avg_miss_latency::total 86630.321911                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85731.451613                      
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88255.102041                      
-system.cpu.l2cache.overall_avg_miss_latency::total 86630.321911                      
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                      
-system.cpu.l2cache.blocked_cycles::no_targets            0                      
-system.cpu.l2cache.blocked::no_mshrs                0                      
-system.cpu.l2cache.blocked::no_targets              0                      
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                      
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                      
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                      
-system.cpu.l2cache.ReadExReq_mshr_misses::total          146                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          620                      
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          620                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          197                      
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          197                      
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          620                      
-system.cpu.l2cache.demand_mshr_misses::cpu.data          343                      
-system.cpu.l2cache.demand_mshr_misses::total          963                      
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          620                      
-system.cpu.l2cache.overall_mshr_misses::cpu.data          343                      
-system.cpu.l2cache.overall_mshr_misses::total          963                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10795000                      
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10795000                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     46953500                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     46953500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     16056500                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     16056500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     46953500                      
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     26851500                      
-system.cpu.l2cache.demand_mshr_miss_latency::total     73805000                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     46953500                      
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     26851500                      
-system.cpu.l2cache.overall_mshr_miss_latency::total     73805000                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                      
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.995185                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                      
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                      
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.996894                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995185                      
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                      
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.996894                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73938.356164                      
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73938.356164                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75731.451613                      
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75731.451613                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81505.076142                      
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81505.076142                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75731.451613                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78284.256560                      
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76640.706127                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75731.451613                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78284.256560                      
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76640.706127                      
-system.cpu.toL2Bus.snoop_filter.tot_requests          973                      
-system.cpu.toL2Bus.snoop_filter.hit_single_requests            9                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                      
-system.cpu.toL2Bus.snoop_filter.tot_snoops            0                      
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                      
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                      
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.cpu.toL2Bus.trans_dist::ReadResp           819                      
-system.cpu.toL2Bus.trans_dist::WritebackClean            7                      
-system.cpu.toL2Bus.trans_dist::ReadExReq          146                      
-system.cpu.toL2Bus.trans_dist::ReadExResp          146                      
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          623                      
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          197                      
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1253                      
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          685                      
-system.cpu.toL2Bus.pkt_count::total              1938                      
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40320                      
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        21888                      
-system.cpu.toL2Bus.pkt_size::total              62208                      
-system.cpu.toL2Bus.snoops                           0                      
-system.cpu.toL2Bus.snoopTraffic                     0                      
-system.cpu.toL2Bus.snoop_fanout::samples          966                      
-system.cpu.toL2Bus.snoop_fanout::mean        0.002070                      
-system.cpu.toL2Bus.snoop_fanout::stdev       0.045478                      
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00%
-system.cpu.toL2Bus.snoop_fanout::0                964     99.79%     99.79%
-system.cpu.toL2Bus.snoop_fanout::1                  2      0.21%    100.00%
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value            0                      
-system.cpu.toL2Bus.snoop_fanout::max_value            1                      
-system.cpu.toL2Bus.snoop_fanout::total            966                      
-system.cpu.toL2Bus.reqLayer0.occupancy         493500                      
-system.cpu.toL2Bus.reqLayer0.utilization          1.8                      
-system.cpu.toL2Bus.respLayer0.occupancy        934500                      
-system.cpu.toL2Bus.respLayer0.utilization          3.4                      
-system.cpu.toL2Bus.respLayer1.occupancy        513000                      
-system.cpu.toL2Bus.respLayer1.utilization          1.9                      
-system.membus.snoop_filter.tot_requests           963                      
-system.membus.snoop_filter.hit_single_requests            0                      
-system.membus.snoop_filter.hit_multi_requests            0                      
-system.membus.snoop_filter.tot_snoops               0                      
-system.membus.snoop_filter.hit_single_snoops            0                      
-system.membus.snoop_filter.hit_multi_snoops            0                      
-system.membus.pwrStateResidencyTicks::UNDEFINED     27117500                      
-system.membus.trans_dist::ReadResp                816                      
-system.membus.trans_dist::ReadExReq               146                      
-system.membus.trans_dist::ReadExResp              146                      
-system.membus.trans_dist::ReadSharedReq           817                      
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1925                      
-system.membus.pkt_count::total                   1925                      
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        61568                      
-system.membus.pkt_size::total                   61568                      
-system.membus.snoops                                0                      
-system.membus.snoopTraffic                          0                      
-system.membus.snoop_fanout::samples               963                      
-system.membus.snoop_fanout::mean                    0                      
-system.membus.snoop_fanout::stdev                   0                      
-system.membus.snoop_fanout::underflows              0      0.00%      0.00%
-system.membus.snoop_fanout::0                     963    100.00%    100.00%
-system.membus.snoop_fanout::1                       0      0.00%    100.00%
-system.membus.snoop_fanout::overflows               0      0.00%    100.00%
-system.membus.snoop_fanout::min_value               0                      
-system.membus.snoop_fanout::max_value               0                      
-system.membus.snoop_fanout::total                 963                      
-system.membus.reqLayer0.occupancy             1169500                      
-system.membus.reqLayer0.utilization               4.3                      
-system.membus.respLayer1.occupancy            5110750                      
-system.membus.respLayer1.utilization             18.8                      
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
deleted file mode 100644
index 1efeb5f..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
+++ /dev/null
@@ -1,265 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.membus.slave[1]
-icache_port=system.membus.slave[0]
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=tests/test-progs/hello/bin/alpha/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr
deleted file mode 100755
index 2f95074..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr
+++ /dev/null
@@ -1,3 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
deleted file mode 100755
index 4e8f563..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
+++ /dev/null
@@ -1,16 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:47
-gem5 executing on e108600-lin, pid 28091
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 461109000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
deleted file mode 100644
index e73b49a..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
+++ /dev/null
@@ -1,417 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000461                       # Number of seconds simulated
-sim_ticks                                   461109000                       # Number of ticks simulated
-final_tick                                  461109000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 260049                       # Simulator instruction rate (inst/s)
-host_op_rate                                   259797                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18548021181                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 634440                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                        6453                       # Number of instructions simulated
-sim_ops                                          6453                       # Number of ops (including micro ops) simulated
-system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
-system.mem_ctrl.bytes_read::cpu.inst            25852                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data             8844                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total               34696                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst        25852                       # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total          25852                       # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_written::cpu.data          6696                       # Number of bytes written to this memory
-system.mem_ctrl.bytes_written::total             6696                       # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst              6463                       # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data              1190                       # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total                 7653                       # Number of read requests responded to by this memory
-system.mem_ctrl.num_writes::cpu.data              865                       # Number of write requests responded to by this memory
-system.mem_ctrl.num_writes::total                 865                       # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst            56064835                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data            19179847                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total               75244682                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst       56064835                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total          56064835                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data           14521512                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total              14521512                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst           56064835                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data           33701359                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total              89766194                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs                         7654                       # Number of read requests accepted
-system.mem_ctrl.writeReqs                         865                       # Number of write requests accepted
-system.mem_ctrl.readBursts                       7654                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrl.writeBursts                       865                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                  477504                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                    12352                       # Total number of bytes read from write queue
-system.mem_ctrl.bytesWritten                     6144                       # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys                    34700                       # Total read bytes from the system interface side
-system.mem_ctrl.bytesWrittenSys                  6696                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                     193                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts                    752                       # Number of DRAM write bursts merged with an existing one
-system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
-system.mem_ctrl.perBankRdBursts::0               1736                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::1                393                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::2                768                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3                800                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4                764                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::5                293                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::6                  6                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::7                 26                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::8                  0                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9                  1                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10               249                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::11               578                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::12               167                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13              1431                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14                91                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15               158                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4                 18                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5                  7                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10                 7                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13                20                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14                44                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
-system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
-system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                      461032000                       # Total gap between requests
-system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2                   6633                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3                   1021                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::4                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::5                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::6                      0                       # Read request sizes (log2)
-system.mem_ctrl.writePktSize::0                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::1                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::2                    56                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::3                   809                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                     7461                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::4                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::5                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::6                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::7                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::8                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::9                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::10                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::11                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::12                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::13                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::14                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::15                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::16                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::17                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::18                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::19                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::20                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::21                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::22                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::23                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::24                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::25                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::26                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::27                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::28                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::29                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::30                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::31                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::0                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::1                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::2                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::3                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::4                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::5                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::6                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::7                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::8                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::9                        1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::10                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::11                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::12                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::13                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::14                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::15                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::16                       1                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::19                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::20                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::21                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::22                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::23                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::24                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::25                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::29                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::30                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::31                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::32                       6                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::36                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::37                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::38                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::39                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::40                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::41                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::42                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::43                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::44                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::45                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::46                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::47                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::48                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::49                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::50                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::51                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::52                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::53                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::54                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::55                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::56                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::57                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::58                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::59                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::60                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          766                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     629.556136                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    420.481555                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    399.288519                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127           144     18.80%     18.80% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           67      8.75%     27.55% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           42      5.48%     33.03% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511           49      6.40%     39.43% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639           40      5.22%     44.65% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767           39      5.09%     49.74% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895           38      4.96%     54.70% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023           34      4.44%     59.14% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151          313     40.86%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           766                       # Bytes accessed per row activation
-system.mem_ctrl.rdPerTurnAround::samples            6                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean            1237                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean    1086.549947                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev     686.122730                       # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::512-639            2     33.33%     33.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1152-1279            2     33.33%     66.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1408-1535            1     16.67%     83.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::2304-2431            1     16.67%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::total              6                       # Reads before turning the bus around for writes
-system.mem_ctrl.wrPerTurnAround::samples            6                       # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::mean              16                       # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::gmean      16.000000                       # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::16                 6    100.00%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::total              6                       # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat                      73323250                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                213217000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                    37305000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                       9827.54                       # Average queueing delay per DRAM burst
-system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 28577.54                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                       1035.56                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                         13.32                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                      75.25                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                      14.52                       # Average system write bandwidth in MiByte/s
-system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          8.19                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      8.09                       # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite                     0.10                       # Data bus utilization in percentage for writes
-system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                       23.97                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                      6701                       # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits                       86                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  89.81                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                 76.11                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                       54118.09                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     89.61                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                   3184440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                   1681185                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                 34164900                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                  130500                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy          36263760.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy              65335680                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy               1899360                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.actPowerDownEnergy        128211240                       # Energy for active power-down per rank (pJ)
-system.mem_ctrl_0.prePowerDownEnergy         12180000                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
-system.mem_ctrl_0.totalEnergy               283051065                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             613.847162                       # Core power per rank (mW)
-system.mem_ctrl_0.totalIdleTime             312833500                       # Total Idle time Per DRAM Rank
-system.mem_ctrl_0.memoryStateTime::IDLE        882000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF       15340000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN     31715250                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT      132053500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN    281118250                       # Time in different power states
-system.mem_ctrl_1.actEnergy                   2313360                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                   1225785                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                 19099500                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                  370620                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy          35649120.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy              44402430                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy               1287360                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.actPowerDownEnergy        129142620                       # Energy for active power-down per rank (pJ)
-system.mem_ctrl_1.prePowerDownEnergy         18055680                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_1.selfRefreshEnergy           8894220                       # Energy for self refresh per rank (pJ)
-system.mem_ctrl_1.totalEnergy               260440695                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             564.812507                       # Core power per rank (mW)
-system.mem_ctrl_1.totalIdleTime             359701750                       # Total Idle time Per DRAM Rank
-system.mem_ctrl_1.memoryStateTime::IDLE       1420000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF       15098000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::SREF      30156500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN     47020500                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT       84176750                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN    283237250                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1190                       # DTB read hits
-system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1197                       # DTB read accesses
-system.cpu.dtb.write_hits                         865                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2055                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2065                       # DTB accesses
-system.cpu.itb.fetch_hits                        6464                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6481                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON       461109000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                           461109                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6453                       # Number of instructions committed
-system.cpu.committedOps                          6453                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6380                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          759                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6380                       # number of integer instructions
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8392                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4621                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2065                       # number of memory refs
-system.cpu.num_load_insts                        1197                       # Number of load instructions
-system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     461109                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                              1060                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                    19      0.29%      0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu                      4376     67.71%     68.00% # Class of executed instruction
-system.cpu.op_class::IntMult                        1      0.02%     68.02% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     68.02% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::MemRead                     1196     18.51%     86.55% # Class of executed instruction
-system.cpu.op_class::MemWrite                     861     13.32%     99.88% # Class of executed instruction
-system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       6463                       # Class of executed instruction
-system.membus.snoop_filter.tot_requests             0                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED    461109000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7654                       # Transaction distribution
-system.membus.trans_dist::ReadResp               7653                       # Transaction distribution
-system.membus.trans_dist::WriteReq                865                       # Transaction distribution
-system.membus.trans_dist::WriteResp               865                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port        12927                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port         4110                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  17037                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port        25852                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port        15540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   41392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples              8519                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    8519    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                8519                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9384000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy           14690000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3572750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
deleted file mode 100644
index 5a1f94c..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
+++ /dev/null
@@ -1,432 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=65536
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.l2bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=16384
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.icache_port
-mem_side=system.l2bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=16384
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=tests/test-progs/hello/bin/alpha/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.l2bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.l2bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=262144
-system=system
-tags=system.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.l2bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.l2cache.mem_side system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr
deleted file mode 100755
index 2f95074..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr
+++ /dev/null
@@ -1,3 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
deleted file mode 100755
index 2e75b8a..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
+++ /dev/null
@@ -1,16 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:46
-gem5 executing on e108600-lin, pid 28074
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 64758000 because target called exit()
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
deleted file mode 100644
index 58d0eea..0000000
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ /dev/null
@@ -1,745 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000065                       # Number of seconds simulated
-sim_ticks                                    64758000                       # Number of ticks simulated
-final_tick                                   64758000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 610635                       # Simulator instruction rate (inst/s)
-host_op_rate                                   610062                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6117087273                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 638532                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        6453                       # Number of instructions simulated
-sim_ops                                          6453                       # Number of ops (including micro ops) simulated
-system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.mem_ctrl.bytes_read::cpu.inst            17792                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data            10752                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total               28544                       # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total          17792                       # Number of instructions bytes read from this memory
-system.mem_ctrl.num_reads::cpu.inst               278                       # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data               168                       # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total                  446                       # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst           274745977                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data           166033540                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total              440779518                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst      274745977                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total         274745977                       # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst          274745977                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data          166033540                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total             440779518                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs                          446                       # Number of read requests accepted
-system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
-system.mem_ctrl.readBursts                        446                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrl.writeBursts                         0                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM                   28544                       # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ                        0                       # Total number of bytes read from write queue
-system.mem_ctrl.bytesWritten                        0                       # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys                    28544                       # Total read bytes from the system interface side
-system.mem_ctrl.bytesWrittenSys                     0                       # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ                       0                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts                      0                       # Number of DRAM write bursts merged with an existing one
-system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
-system.mem_ctrl.perBankRdBursts::0                 62                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::1                 26                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::2                 24                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3                 43                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4                 40                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::5                 17                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::6                  1                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::7                  3                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::8                  0                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9                  1                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10                19                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::11                23                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::12                14                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13               116                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14                45                       # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15                12                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
-system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
-system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
-system.mem_ctrl.totGap                       64501000                       # Total gap between requests
-system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::4                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::5                      0                       # Read request sizes (log2)
-system.mem_ctrl.readPktSize::6                    446                       # Read request sizes (log2)
-system.mem_ctrl.writePktSize::0                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::1                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::2                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::3                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
-system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0                      446                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::4                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::5                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::6                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::7                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::8                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::9                        0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::10                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::11                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::12                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::13                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::14                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::15                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::16                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::17                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::18                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::19                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::20                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::21                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::22                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::23                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::24                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::25                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::26                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::27                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::28                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::29                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::30                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::31                       0                       # What read queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::0                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::1                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::2                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::3                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::4                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::5                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::6                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::7                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::8                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::9                        0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::10                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::11                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::12                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::13                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::14                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::15                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::16                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::19                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::20                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::21                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::22                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::23                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::24                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::25                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::29                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::30                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::31                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::32                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::36                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::37                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::38                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::39                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::40                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::41                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::42                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::43                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::44                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::45                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::46                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::47                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::48                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::49                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::50                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::51                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::52                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::53                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::54                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::55                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::56                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::57                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::58                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::59                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::60                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples          105                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean     264.533333                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean    181.831163                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev    249.307389                       # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127            27     25.71%     25.71% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255           40     38.10%     63.81% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383           10      9.52%     73.33% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511            9      8.57%     81.90% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639            7      6.67%     88.57% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767            6      5.71%     94.29% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895            1      0.95%     95.24% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151            5      4.76%    100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total           105                       # Bytes accessed per row activation
-system.mem_ctrl.totQLat                       6134000                       # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat                 14496500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat                     2230000                       # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat                      13753.36                       # Average queueing delay per DRAM burst
-system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat                 32503.36                       # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW                        440.78                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys                     440.78                       # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
-system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil                          3.44                       # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead                      3.44                       # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
-system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits                       337                       # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate                  75.56                       # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
-system.mem_ctrl.avgGap                      144621.08                       # Average gap between requests
-system.mem_ctrl.pageHitRate                     75.56                       # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy                    314160                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy                    163185                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy                  1542240                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy               3812160                       # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy                131040                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.actPowerDownEnergy         22575420                       # Energy for active power-down per rank (pJ)
-system.mem_ctrl_0.prePowerDownEnergy          2515200                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
-system.mem_ctrl_0.totalEnergy                35970525                       # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower             555.454282                       # Core power per rank (mW)
-system.mem_ctrl_0.totalIdleTime              55623250                       # Total Idle time Per DRAM Rank
-system.mem_ctrl_0.memoryStateTime::IDLE         77000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF        2080000                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN      6549500                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT        6531250                       # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN     49520250                       # Time in different power states
-system.mem_ctrl_1.actEnergy                    464100                       # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy                    235290                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy                  1642200                       # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy          4917120.000000                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy               4174680                       # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy                251520                       # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.actPowerDownEnergy         24338430                       # Energy for active power-down per rank (pJ)
-system.mem_ctrl_1.prePowerDownEnergy           604800                       # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
-system.mem_ctrl_1.totalEnergy                36628140                       # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower             565.609126                       # Core power per rank (mW)
-system.mem_ctrl_1.totalIdleTime              54728750                       # Total Idle time Per DRAM Rank
-system.mem_ctrl_1.memoryStateTime::IDLE        283000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF        2080000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN      1573250                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT        7457000                       # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN     53364750                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1190                       # DTB read hits
-system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1197                       # DTB read accesses
-system.cpu.dtb.write_hits                         865                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2055                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2065                       # DTB accesses
-system.cpu.itb.fetch_hits                        6464                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6481                       # ITB accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.workload.numSyscalls                    17                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON        64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                            64758                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6453                       # Number of instructions committed
-system.cpu.committedOps                          6453                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6380                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          759                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6380                       # number of integer instructions
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8392                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4621                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2065                       # number of memory refs
-system.cpu.num_load_insts                        1197                       # Number of load instructions
-system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      64758                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                              1060                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                    19      0.29%      0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu                      4376     67.71%     68.00% # Class of executed instruction
-system.cpu.op_class::IntMult                        1      0.02%     68.02% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     68.02% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       2      0.03%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatMisc                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.05% # Class of executed instruction
-system.cpu.op_class::MemRead                     1196     18.51%     86.55% # Class of executed instruction
-system.cpu.op_class::MemWrite                     861     13.32%     99.88% # Class of executed instruction
-system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       6463                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.399751                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1887                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.232143                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   104.399751                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.101953                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.101953                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.164062                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4278                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4278                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data         1095                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1095                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1887                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1887                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1887                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1887                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           73                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
-system.cpu.dcache.overall_misses::total           168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10261000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10261000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      7802000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      7802000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     18063000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     18063000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     18063000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     18063000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1190                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1190                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2055                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2055                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2055                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2055                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079832                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.079832                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.081752                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081752                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.081752                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081752                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 107517.857143                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 107517.857143                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     10071000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     10071000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7656000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7656000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     17727000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     17727000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     17727000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     17727000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.079832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.079832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081752                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.081752                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081752                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.081752                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements                62                       # number of replacements
-system.cpu.icache.tags.tagsinuse           113.445692                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                6183                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               281                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.003559                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   113.445692                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.443147                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.443147                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          219                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.855469                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             13209                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            13209                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst         6183                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6183                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6183                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6183                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6183                       # number of overall hits
-system.cpu.icache.overall_hits::total            6183                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          281                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           281                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          281                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            281                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          281                       # number of overall misses
-system.cpu.icache.overall_misses::total           281                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     30557000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30557000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     30557000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30557000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     30557000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30557000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6464                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6464                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6464                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6464                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6464                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6464                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043472                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.043472                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.043472                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.043472                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.043472                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.043472                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 108743.772242                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 108743.772242                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          281                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          281                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          281                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          281                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          281                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     29995000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     29995000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     29995000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     29995000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     29995000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     29995000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043472                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.043472                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043472                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.043472                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242                       # average overall mshr miss latency
-system.l2bus.snoop_filter.tot_requests            511                       # Total number of requests made to the snoop filter.
-system.l2bus.snoop_filter.hit_single_requests           63                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
-system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.l2bus.trans_dist::ReadResp                 376                       # Transaction distribution
-system.l2bus.trans_dist::CleanEvict                62                       # Transaction distribution
-system.l2bus.trans_dist::ReadExReq                 73                       # Transaction distribution
-system.l2bus.trans_dist::ReadExResp                73                       # Transaction distribution
-system.l2bus.trans_dist::ReadSharedReq            376                       # Transaction distribution
-system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          624                       # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side          336                       # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count::total                     960                       # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side        17984                       # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.pkt_size::total                    28736                       # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.snoops                                 0                       # Total snoops (count)
-system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
-system.l2bus.snoop_fanout::samples                449                       # Request fanout histogram
-system.l2bus.snoop_fanout::mean              0.002227                       # Request fanout histogram
-system.l2bus.snoop_fanout::stdev             0.047193                       # Request fanout histogram
-system.l2bus.snoop_fanout::underflows               0      0.00%      0.00% # Request fanout histogram
-system.l2bus.snoop_fanout::0                      448     99.78%     99.78% # Request fanout histogram
-system.l2bus.snoop_fanout::1                        1      0.22%    100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::2                        0      0.00%    100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::overflows                0      0.00%    100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::min_value                0                       # Request fanout histogram
-system.l2bus.snoop_fanout::max_value                1                       # Request fanout histogram
-system.l2bus.snoop_fanout::total                  449                       # Request fanout histogram
-system.l2bus.reqLayer0.occupancy               511000                       # Layer occupancy (ticks)
-system.l2bus.reqLayer0.utilization                0.8                       # Layer utilization (%)
-system.l2bus.respLayer0.occupancy              843000                       # Layer occupancy (ticks)
-system.l2bus.respLayer0.utilization               1.3                       # Layer utilization (%)
-system.l2bus.respLayer1.occupancy              504000                       # Layer occupancy (ticks)
-system.l2bus.respLayer1.utilization               0.8                       # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.l2cache.tags.replacements                    0                       # number of replacements
-system.l2cache.tags.tagsinuse              232.606847                       # Cycle average of tags in use
-system.l2cache.tags.total_refs                     65                       # Total number of references to valid blocks.
-system.l2cache.tags.sampled_refs                  446                       # Sample count of references to valid blocks.
-system.l2cache.tags.avg_refs                 0.145740                       # Average number of references to valid blocks.
-system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst   128.152617                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data   104.454231                       # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst     0.031287                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data     0.025502                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total       0.056789                       # Average percentage of cache occupancy
-system.l2cache.tags.occ_task_id_blocks::1024          446                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::1          384                       # Occupied blocks per task id
-system.l2cache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
-system.l2cache.tags.tag_accesses                 4534                       # Number of tag accesses
-system.l2cache.tags.data_accesses                4534                       # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.l2cache.ReadSharedReq_hits::cpu.inst            3                       # number of ReadSharedReq hits
-system.l2cache.ReadSharedReq_hits::total            3                       # number of ReadSharedReq hits
-system.l2cache.demand_hits::cpu.inst                3                       # number of demand (read+write) hits
-system.l2cache.demand_hits::total                   3                       # number of demand (read+write) hits
-system.l2cache.overall_hits::cpu.inst               3                       # number of overall hits
-system.l2cache.overall_hits::total                  3                       # number of overall hits
-system.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
-system.l2cache.ReadExReq_misses::total             73                       # number of ReadExReq misses
-system.l2cache.ReadSharedReq_misses::cpu.inst          278                       # number of ReadSharedReq misses
-system.l2cache.ReadSharedReq_misses::cpu.data           95                       # number of ReadSharedReq misses
-system.l2cache.ReadSharedReq_misses::total          373                       # number of ReadSharedReq misses
-system.l2cache.demand_misses::cpu.inst            278                       # number of demand (read+write) misses
-system.l2cache.demand_misses::cpu.data            168                       # number of demand (read+write) misses
-system.l2cache.demand_misses::total               446                       # number of demand (read+write) misses
-system.l2cache.overall_misses::cpu.inst           278                       # number of overall misses
-system.l2cache.overall_misses::cpu.data           168                       # number of overall misses
-system.l2cache.overall_misses::total              446                       # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data      7437000                       # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total      7437000                       # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst     29087000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data      9786000                       # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total     38873000                       # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst     29087000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data     17223000                       # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total     46310000                       # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst     29087000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data     17223000                       # number of overall miss cycles
-system.l2cache.overall_miss_latency::total     46310000                       # number of overall miss cycles
-system.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
-system.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::cpu.inst          281                       # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::cpu.data           95                       # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::total          376                       # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.demand_accesses::cpu.inst          281                       # number of demand (read+write) accesses
-system.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
-system.l2cache.demand_accesses::total             449                       # number of demand (read+write) accesses
-system.l2cache.overall_accesses::cpu.inst          281                       # number of overall (read+write) accesses
-system.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
-system.l2cache.overall_accesses::total            449                       # number of overall (read+write) accesses
-system.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.l2cache.ReadSharedReq_miss_rate::cpu.inst     0.989324                       # miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_miss_rate::total     0.992021                       # miss rate for ReadSharedReq accesses
-system.l2cache.demand_miss_rate::cpu.inst     0.989324                       # miss rate for demand accesses
-system.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.l2cache.demand_miss_rate::total       0.993318                       # miss rate for demand accesses
-system.l2cache.overall_miss_rate::cpu.inst     0.989324                       # miss rate for overall accesses
-system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.l2cache.overall_miss_rate::total      0.993318                       # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329                       # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329                       # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316                       # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177                       # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143                       # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 103834.080717                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143                       # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 103834.080717                       # average overall miss latency
-system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
-system.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          278                       # number of ReadSharedReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::cpu.data           95                       # number of ReadSharedReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::total          373                       # number of ReadSharedReq MSHR misses
-system.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
-system.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
-system.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
-system.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
-system.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
-system.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5977000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total      5977000                       # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     23527000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7886000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total     31413000                       # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst     23527000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data     13863000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total     37390000                       # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst     23527000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data     13863000                       # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total     37390000                       # number of overall MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.989324                       # mshr miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::total     0.992021                       # mshr miss rate for ReadSharedReq accesses
-system.l2cache.demand_mshr_miss_rate::cpu.inst     0.989324                       # mshr miss rate for demand accesses
-system.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.l2cache.demand_mshr_miss_rate::total     0.993318                       # mshr miss rate for demand accesses
-system.l2cache.overall_mshr_miss_rate::cpu.inst     0.989324                       # mshr miss rate for overall accesses
-system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.l2cache.overall_mshr_miss_rate::total     0.993318                       # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329                       # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329                       # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316                       # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177                       # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143                       # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143                       # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717                       # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests           446                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED     64758000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp                373                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           373                       # Transaction distribution
-system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port          892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   28544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples               446                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     446    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 446                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              446000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2377500                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              3.7                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/EMPTY b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/EMPTY
+++ /dev/null
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/EMPTY b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/EMPTY
+++ /dev/null
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/EMPTY b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/EMPTY
+++ /dev/null
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/EMPTY b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/EMPTY
+++ /dev/null
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/EMPTY b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/EMPTY
deleted file mode 100644
index e69de29..0000000
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/EMPTY
+++ /dev/null