| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 1.910457 # Number of seconds simulated |
| sim_ticks 1910457097500 # Number of ticks simulated |
| final_tick 1910457097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 237868 # Simulator instruction rate (inst/s) |
| host_op_rate 237868 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 8017235800 # Simulator tick rate (ticks/s) |
| host_mem_usage 340828 # Number of bytes of host memory used |
| host_seconds 238.29 # Real time elapsed on the host |
| sim_insts 56682446 # Number of instructions simulated |
| sim_ops 56682446 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu0.inst 856512 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu0.data 24438912 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu1.inst 120704 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu1.data 888384 # Number of bytes read from this memory |
| system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 26305472 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu0.inst 856512 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::cpu1.inst 120704 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 977216 # Number of instructions bytes read from this memory |
| system.physmem.bytes_written::writebacks 7909632 # Number of bytes written to this memory |
| system.physmem.bytes_written::total 7909632 # Number of bytes written to this memory |
| system.physmem.num_reads::cpu0.inst 13383 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu0.data 381858 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu1.inst 1886 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu1.data 13881 # Number of read requests responded to by this memory |
| system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 411023 # Number of read requests responded to by this memory |
| system.physmem.num_writes::writebacks 123588 # Number of write requests responded to by this memory |
| system.physmem.num_writes::total 123588 # Number of write requests responded to by this memory |
| system.physmem.bw_read::cpu0.inst 448328 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu0.data 12792180 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu1.inst 63181 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu1.data 465011 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::tsunami.ide 502 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 13769203 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu0.inst 448328 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu1.inst 63181 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 511509 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::writebacks 4140178 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::total 4140178 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::writebacks 4140178 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu0.inst 448328 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu0.data 12792180 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu1.inst 63181 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu1.data 465011 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::tsunami.ide 502 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 17909381 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 411023 # Number of read requests accepted |
| system.physmem.writeReqs 123588 # Number of write requests accepted |
| system.physmem.readBursts 411023 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 123588 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 26298624 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 7907712 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 26305472 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 7909632 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 26243 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 25982 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 25968 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 25688 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 25576 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 25569 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 25629 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 25342 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 25591 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 25697 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 25920 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 25515 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 26076 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 25417 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 25094 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 25609 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 8586 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 8089 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 7939 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 7426 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 7272 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 7413 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 7547 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 7156 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 7533 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 7641 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 7810 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 7729 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 8256 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 7847 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 7516 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 7798 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 69 # Number of times write queue was full causing retry |
| system.physmem.totGap 1910452747500 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 411023 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 123588 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 316637 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 38767 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 30209 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 25132 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 134 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 6 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 1518 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 2732 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 3319 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 4343 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 5637 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 7604 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 8137 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 7914 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 7224 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 7343 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 7491 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 7730 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 6507 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 6752 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 904 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 514 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 331 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 263 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 295 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 286 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 315 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 288 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 326 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 381 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 369 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 277 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 290 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 318 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 343 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 249 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 240 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 310 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 241 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 381 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 395 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 248 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 148 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 64267 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 532.249522 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 325.147595 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 415.887517 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 14293 22.24% 22.24% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 11517 17.92% 40.16% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 5102 7.94% 48.10% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 2862 4.45% 52.55% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 2222 3.46% 56.01% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 1875 2.92% 58.93% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 1935 3.01% 61.94% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 1643 2.56% 64.49% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 22818 35.51% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 64267 # Bytes accessed per row activation |
| system.physmem.rdPerTurnAround::samples 5506 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::mean 74.626952 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::stdev 2826.578445 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::0-8191 5503 99.95% 99.95% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::total 5506 # Reads before turning the bus around for writes |
| system.physmem.wrPerTurnAround::samples 5506 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::mean 22.440610 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::gmean 18.769678 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::stdev 24.128904 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::16-23 4988 90.59% 90.59% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::24-31 40 0.73% 91.32% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::32-39 160 2.91% 94.22% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::40-47 10 0.18% 94.41% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::48-55 4 0.07% 94.48% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::56-63 18 0.33% 94.81% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::64-71 5 0.09% 94.90% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::72-79 6 0.11% 95.01% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::80-87 35 0.64% 95.64% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::88-95 4 0.07% 95.71% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::96-103 137 2.49% 98.20% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::104-111 15 0.27% 98.47% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::112-119 13 0.24% 98.71% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::128-135 8 0.15% 98.91% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::136-143 3 0.05% 98.96% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::144-151 5 0.09% 99.06% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::152-159 3 0.05% 99.11% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::176-183 9 0.16% 99.38% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::184-191 10 0.18% 99.56% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::192-199 9 0.16% 99.73% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::216-223 8 0.15% 99.89% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::224-231 3 0.05% 99.95% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::total 5506 # Writes before turning the bus around for reads |
| system.physmem.totQLat 8133947000 # Total ticks spent queuing |
| system.physmem.totMemAccLat 15838622000 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 2054580000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 19794.67 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 38544.67 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 0.14 # Data bus utilization in percentage |
| system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 2.17 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 27.12 # Average write queue length when enqueuing |
| system.physmem.readRowHits 370641 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 99565 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate 80.56 # Row buffer hit rate for writes |
| system.physmem.avgGap 3573538.04 # Average gap between requests |
| system.physmem.pageHitRate 87.97 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 228629940 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 121519695 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 320654160 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 3862397760.000001 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 4332596790 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 252811200 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 8421848610 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 4670504160 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 449339904270 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 473022982485 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 247.596757 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 1900281265750 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 402747000 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 1640746000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 1869662817000 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 12162830000 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 8118960750 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 18468996750 # Time in different power states |
| system.physmem_1.actEnergy 230243580 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 122373570 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 1463121660 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 324318600 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 3740699040.000001 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 4231975260 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 230624160 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 8237523150 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 4445714880 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 449624008125 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 472652324325 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 247.402742 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 1900567958250 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 356565750 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 1589032000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 1870929942000 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 11577456000 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 7939162500 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 18064939250 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.branchPred.lookups 16804357 # Number of BP lookups |
| system.cpu0.branchPred.condPredicted 14368910 # Number of conditional branches predicted |
| system.cpu0.branchPred.condIncorrect 476654 # Number of conditional branches incorrect |
| system.cpu0.branchPred.BTBLookups 10787243 # Number of BTB lookups |
| system.cpu0.branchPred.BTBHits 4777357 # Number of BTB hits |
| system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu0.branchPred.BTBHitPct 44.287099 # BTB Hit Percentage |
| system.cpu0.branchPred.usedRAS 929095 # Number of times the RAS was used to get a target. |
| system.cpu0.branchPred.RASInCorrect 33008 # Number of incorrect RAS predictions. |
| system.cpu0.branchPred.indirectLookups 5112942 # Number of indirect predictor lookups. |
| system.cpu0.branchPred.indirectHits 499455 # Number of indirect target hits. |
| system.cpu0.branchPred.indirectMisses 4613487 # Number of indirect misses. |
| system.cpu0.branchPredindirectMispredicted 206250 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu0.dtb.fetch_hits 0 # ITB hits |
| system.cpu0.dtb.fetch_misses 0 # ITB misses |
| system.cpu0.dtb.fetch_acv 0 # ITB acv |
| system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| system.cpu0.dtb.read_hits 9429395 # DTB read hits |
| system.cpu0.dtb.read_misses 34826 # DTB read misses |
| system.cpu0.dtb.read_acv 601 # DTB read access violations |
| system.cpu0.dtb.read_accesses 567385 # DTB read accesses |
| system.cpu0.dtb.write_hits 5710239 # DTB write hits |
| system.cpu0.dtb.write_misses 8500 # DTB write misses |
| system.cpu0.dtb.write_acv 413 # DTB write access violations |
| system.cpu0.dtb.write_accesses 185113 # DTB write accesses |
| system.cpu0.dtb.data_hits 15139634 # DTB hits |
| system.cpu0.dtb.data_misses 43326 # DTB misses |
| system.cpu0.dtb.data_acv 1014 # DTB access violations |
| system.cpu0.dtb.data_accesses 752498 # DTB accesses |
| system.cpu0.itb.fetch_hits 1313411 # ITB hits |
| system.cpu0.itb.fetch_misses 6916 # ITB misses |
| system.cpu0.itb.fetch_acv 613 # ITB acv |
| system.cpu0.itb.fetch_accesses 1320327 # ITB accesses |
| system.cpu0.itb.read_hits 0 # DTB read hits |
| system.cpu0.itb.read_misses 0 # DTB read misses |
| system.cpu0.itb.read_acv 0 # DTB read access violations |
| system.cpu0.itb.read_accesses 0 # DTB read accesses |
| system.cpu0.itb.write_hits 0 # DTB write hits |
| system.cpu0.itb.write_misses 0 # DTB write misses |
| system.cpu0.itb.write_acv 0 # DTB write access violations |
| system.cpu0.itb.write_accesses 0 # DTB write accesses |
| system.cpu0.itb.data_hits 0 # DTB hits |
| system.cpu0.itb.data_misses 0 # DTB misses |
| system.cpu0.itb.data_acv 0 # DTB access violations |
| system.cpu0.itb.data_accesses 0 # DTB accesses |
| system.cpu0.numPwrStateTransitions 12957 # Number of power state transitions |
| system.cpu0.pwrStateClkGateDist::samples 6479 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::mean 285646442.815249 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::stdev 440880288.422179 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::1000-5e+10 6479 100.00% 100.00% # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::min_value 39000 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateClkGateDist::total 6479 # Distribution of time spent in the clock gated state |
| system.cpu0.pwrStateResidencyTicks::ON 59753794500 # Cumulative time (in ticks) in various power states |
| system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000 # Cumulative time (in ticks) in various power states |
| system.cpu0.numCycles 119514068 # number of cpu cycles simulated |
| system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu0.fetch.icacheStallCycles 25767559 # Number of cycles fetch is stalled on an Icache miss |
| system.cpu0.fetch.Insts 73719684 # Number of instructions fetch has processed |
| system.cpu0.fetch.Branches 16804357 # Number of branches that fetch encountered |
| system.cpu0.fetch.predictedBranches 6205907 # Number of branches that fetch has predicted taken |
| system.cpu0.fetch.Cycles 86932839 # Number of cycles fetch has run and was not squashing or blocked |
| system.cpu0.fetch.SquashCycles 1362768 # Number of cycles fetch has spent squashing |
| system.cpu0.fetch.TlbCycles 60 # Number of cycles fetch has spent waiting for tlb |
| system.cpu0.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| system.cpu0.fetch.PendingTrapStallCycles 137457 # Number of stall cycles due to pending traps |
| system.cpu0.fetch.PendingQuiesceStallCycles 417781 # Number of stall cycles due to pending quiesce instructions |
| system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR |
| system.cpu0.fetch.CacheLines 8508507 # Number of cache lines fetched |
| system.cpu0.fetch.IcacheSquashes 323806 # Number of outstanding Icache misses that were squashed |
| system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed |
| system.cpu0.fetch.rateDist::samples 113967656 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::mean 0.646847 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::stdev 1.957898 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::0 100279992 87.99% 87.99% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::1 883136 0.77% 88.76% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::2 1879288 1.65% 90.41% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::3 773699 0.68% 91.09% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::4 2621733 2.30% 93.39% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::5 582123 0.51% 93.90% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::6 690580 0.61% 94.51% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::7 840992 0.74% 95.25% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::8 5416113 4.75% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.rateDist::total 113967656 # Number of instructions fetched each cycle (Total) |
| system.cpu0.fetch.branchRate 0.140606 # Number of branch fetches per cycle |
| system.cpu0.fetch.rate 0.616829 # Number of inst fetches per cycle |
| system.cpu0.decode.IdleCycles 20688539 # Number of cycles decode is idle |
| system.cpu0.decode.BlockedCycles 82043348 # Number of cycles decode is blocked |
| system.cpu0.decode.RunCycles 8777506 # Number of cycles decode is running |
| system.cpu0.decode.UnblockCycles 1804992 # Number of cycles decode is unblocking |
| system.cpu0.decode.SquashCycles 653270 # Number of cycles decode is squashing |
| system.cpu0.decode.BranchResolved 4633985 # Number of times decode resolved a branch |
| system.cpu0.decode.BranchMispred 29119 # Number of times decode detected a branch misprediction |
| system.cpu0.decode.DecodedInsts 64001211 # Number of instructions handled by decode |
| system.cpu0.decode.SquashedInsts 84558 # Number of squashed instructions handled by decode |
| system.cpu0.rename.SquashCycles 653270 # Number of cycles rename is squashing |
| system.cpu0.rename.IdleCycles 21557209 # Number of cycles rename is idle |
| system.cpu0.rename.BlockCycles 55702323 # Number of cycles rename is blocking |
| system.cpu0.rename.serializeStallCycles 17600356 # count of cycles rename stalled for serializing inst |
| system.cpu0.rename.RunCycles 9645124 # Number of cycles rename is running |
| system.cpu0.rename.UnblockCycles 8809372 # Number of cycles rename is unblocking |
| system.cpu0.rename.RenamedInsts 61498566 # Number of instructions processed by rename |
| system.cpu0.rename.ROBFullEvents 199219 # Number of times rename has blocked due to ROB full |
| system.cpu0.rename.IQFullEvents 2004403 # Number of times rename has blocked due to IQ full |
| system.cpu0.rename.LQFullEvents 243805 # Number of times rename has blocked due to LQ full |
| system.cpu0.rename.SQFullEvents 4929982 # Number of times rename has blocked due to SQ full |
| system.cpu0.rename.RenamedOperands 41484246 # Number of destination operands rename has renamed |
| system.cpu0.rename.RenameLookups 74256527 # Number of register rename lookups that rename has made |
| system.cpu0.rename.int_rename_lookups 74125426 # Number of integer rename lookups |
| system.cpu0.rename.fp_rename_lookups 122370 # Number of floating rename lookups |
| system.cpu0.rename.CommittedMaps 33821902 # Number of HB maps that are committed |
| system.cpu0.rename.UndoneMaps 7662344 # Number of HB maps that are undone due to squashing |
| system.cpu0.rename.serializingInsts 1423361 # count of serializing insts renamed |
| system.cpu0.rename.tempSerializingInsts 232902 # count of temporary serializing insts renamed |
| system.cpu0.rename.skidInsts 12334048 # count of insts added to the skid buffer |
| system.cpu0.memDep0.insertedLoads 9834851 # Number of loads inserted to the mem dependence unit. |
| system.cpu0.memDep0.insertedStores 6076556 # Number of stores inserted to the mem dependence unit. |
| system.cpu0.memDep0.conflictingLoads 1449838 # Number of conflicting loads. |
| system.cpu0.memDep0.conflictingStores 941199 # Number of conflicting stores. |
| system.cpu0.iq.iqInstsAdded 54338035 # Number of instructions added to the IQ (excludes non-spec) |
| system.cpu0.iq.iqNonSpecInstsAdded 1857223 # Number of non-speculative instructions added to the IQ |
| system.cpu0.iq.iqInstsIssued 52670686 # Number of instructions issued |
| system.cpu0.iq.iqSquashedInstsIssued 76725 # Number of squashed instructions issued |
| system.cpu0.iq.iqSquashedInstsExamined 9465955 # Number of squashed instructions iterated over during squash; mainly for profiling |
| system.cpu0.iq.iqSquashedOperandsExamined 4150833 # Number of squashed operands that are examined and possibly removed from graph |
| system.cpu0.iq.iqSquashedNonSpecRemoved 1293033 # Number of squashed non-spec instructions that were removed |
| system.cpu0.iq.issued_per_cycle::samples 113967656 # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::mean 0.462155 # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::stdev 1.203590 # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::0 92547755 81.21% 81.21% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::1 9157312 8.04% 89.24% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::2 3826452 3.36% 92.60% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::3 2741793 2.41% 95.00% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::4 2858470 2.51% 97.51% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::5 1410754 1.24% 98.75% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::6 945179 0.83% 99.58% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::7 363161 0.32% 99.90% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::8 116780 0.10% 100.00% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| system.cpu0.iq.issued_per_cycle::total 113967656 # Number of insts issued each cycle |
| system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::IntAlu 167135 16.69% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::MemRead 489044 48.84% 65.53% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::MemWrite 297041 29.67% 95.20% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatMemRead 26511 2.65% 97.85% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::FloatMemWrite 21568 2.15% 100.00% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu0.iq.FU_type_0::No_OpClass 2539 0.00% 0.00% # Type of FU issued |
| system.cpu0.iq.FU_type_0::IntAlu 36140522 68.62% 68.62% # Type of FU issued |
| system.cpu0.iq.FU_type_0::IntMult 55958 0.11% 68.73% # Type of FU issued |
| system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatAdd 25396 0.05% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued |
| system.cpu0.iq.FU_type_0::MemRead 9743290 18.50% 87.28% # Type of FU issued |
| system.cpu0.iq.FU_type_0::MemWrite 5689891 10.80% 98.08% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatMemRead 122252 0.23% 98.31% # Type of FU issued |
| system.cpu0.iq.FU_type_0::FloatMemWrite 110721 0.21% 98.52% # Type of FU issued |
| system.cpu0.iq.FU_type_0::IprAccess 778850 1.48% 100.00% # Type of FU issued |
| system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| system.cpu0.iq.FU_type_0::total 52670686 # Type of FU issued |
| system.cpu0.iq.rate 0.440707 # Inst issue rate |
| system.cpu0.iq.fu_busy_cnt 1001299 # FU busy when requested |
| system.cpu0.iq.fu_busy_rate 0.019011 # FU busy rate (busy events/executed inst) |
| system.cpu0.iq.int_inst_queue_reads 219818324 # Number of integer instruction queue reads |
| system.cpu0.iq.int_inst_queue_writes 65405263 # Number of integer instruction queue writes |
| system.cpu0.iq.int_inst_queue_wakeup_accesses 50914307 # Number of integer instruction queue wakeup accesses |
| system.cpu0.iq.fp_inst_queue_reads 568728 # Number of floating instruction queue reads |
| system.cpu0.iq.fp_inst_queue_writes 273845 # Number of floating instruction queue writes |
| system.cpu0.iq.fp_inst_queue_wakeup_accesses 257541 # Number of floating instruction queue wakeup accesses |
| system.cpu0.iq.int_alu_accesses 53361731 # Number of integer alu accesses |
| system.cpu0.iq.fp_alu_accesses 307715 # Number of floating point alu accesses |
| system.cpu0.iew.lsq.thread0.forwLoads 607759 # Number of loads that had data forwarded from stores |
| system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| system.cpu0.iew.lsq.thread0.squashedLoads 1969497 # Number of loads squashed |
| system.cpu0.iew.lsq.thread0.ignoredResponses 4520 # Number of memory responses ignored because the instruction is squashed |
| system.cpu0.iew.lsq.thread0.memOrderViolation 18416 # Number of memory ordering violations |
| system.cpu0.iew.lsq.thread0.squashedStores 673256 # Number of stores squashed |
| system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| system.cpu0.iew.lsq.thread0.rescheduledLoads 18394 # Number of loads that were rescheduled |
| system.cpu0.iew.lsq.thread0.cacheBlocked 367969 # Number of times an access to memory failed due to the cache being blocked |
| system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| system.cpu0.iew.iewSquashCycles 653270 # Number of cycles IEW is squashing |
| system.cpu0.iew.iewBlockCycles 52238307 # Number of cycles IEW is blocking |
| system.cpu0.iew.iewUnblockCycles 1038475 # Number of cycles IEW is unblocking |
| system.cpu0.iew.iewDispatchedInsts 59749161 # Number of instructions dispatched to IQ |
| system.cpu0.iew.iewDispSquashedInsts 168806 # Number of squashed instructions skipped by dispatch |
| system.cpu0.iew.iewDispLoadInsts 9834851 # Number of dispatched load instructions |
| system.cpu0.iew.iewDispStoreInsts 6076556 # Number of dispatched store instructions |
| system.cpu0.iew.iewDispNonSpecInsts 1644704 # Number of dispatched non-speculative instructions |
| system.cpu0.iew.iewIQFullEvents 40383 # Number of times the IQ has become full, causing a stall |
| system.cpu0.iew.iewLSQFullEvents 797635 # Number of times the LSQ has become full, causing a stall |
| system.cpu0.iew.memOrderViolationEvents 18416 # Number of memory order violations |
| system.cpu0.iew.predictedTakenIncorrect 191736 # Number of branches that were predicted taken incorrectly |
| system.cpu0.iew.predictedNotTakenIncorrect 507842 # Number of branches that were predicted not taken incorrectly |
| system.cpu0.iew.branchMispredicts 699578 # Number of branch mispredicts detected at execute |
| system.cpu0.iew.iewExecutedInsts 51971663 # Number of executed instructions |
| system.cpu0.iew.iewExecLoadInsts 9489993 # Number of load instructions executed |
| system.cpu0.iew.iewExecSquashedInsts 699023 # Number of squashed instructions skipped in execute |
| system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| system.cpu0.iew.exec_nop 3553903 # number of nop insts executed |
| system.cpu0.iew.exec_refs 15226009 # number of memory reference insts executed |
| system.cpu0.iew.exec_branches 8258878 # Number of branches executed |
| system.cpu0.iew.exec_stores 5736016 # Number of stores executed |
| system.cpu0.iew.exec_rate 0.434858 # Inst execution rate |
| system.cpu0.iew.wb_sent 51356635 # cumulative count of insts sent to commit |
| system.cpu0.iew.wb_count 51171848 # cumulative count of insts written-back |
| system.cpu0.iew.wb_producers 26241416 # num instructions producing a value |
| system.cpu0.iew.wb_consumers 36276103 # num instructions consuming a value |
| system.cpu0.iew.wb_rate 0.428166 # insts written-back per cycle |
| system.cpu0.iew.wb_fanout 0.723380 # average fanout of values written-back |
| system.cpu0.commit.commitSquashedInsts 9976632 # The number of squashed insts skipped by commit |
| system.cpu0.commit.commitNonSpecStalls 564190 # The number of times commit has been forced to stall to communicate backwards |
| system.cpu0.commit.branchMispredicts 625296 # The number of times a branch was mispredicted |
| system.cpu0.commit.committed_per_cycle::samples 112216183 # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::mean 0.442120 # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::stdev 1.363987 # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::0 94653327 84.35% 84.35% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::1 6985358 6.22% 90.57% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::2 3782709 3.37% 93.94% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::3 2004229 1.79% 95.73% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::4 1568389 1.40% 97.13% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::5 570810 0.51% 97.64% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::6 418508 0.37% 98.01% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::7 451920 0.40% 98.41% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::8 1780933 1.59% 100.00% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| system.cpu0.commit.committed_per_cycle::total 112216183 # Number of insts commited each cycle |
| system.cpu0.commit.committedInsts 49613021 # Number of instructions committed |
| system.cpu0.commit.committedOps 49613021 # Number of ops (including micro ops) committed |
| system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| system.cpu0.commit.refs 13268654 # Number of memory references committed |
| system.cpu0.commit.loads 7865354 # Number of loads committed |
| system.cpu0.commit.membars 192328 # Number of memory barriers committed |
| system.cpu0.commit.branches 7511599 # Number of branches committed |
| system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. |
| system.cpu0.commit.int_insts 45921534 # Number of committed integer instructions. |
| system.cpu0.commit.function_calls 632359 # Number of function calls committed. |
| system.cpu0.commit.op_class_0::No_OpClass 2886254 5.82% 5.82% # Class of committed instruction |
| system.cpu0.commit.op_class_0::IntAlu 32400169 65.31% 71.12% # Class of committed instruction |
| system.cpu0.commit.op_class_0::IntMult 54625 0.11% 71.23% # Class of committed instruction |
| system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.29% # Class of committed instruction |
| system.cpu0.commit.op_class_0::MemRead 7944499 16.01% 87.30% # Class of committed instruction |
| system.cpu0.commit.op_class_0::MemWrite 5299897 10.68% 97.98% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction |
| system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction |
| system.cpu0.commit.op_class_0::IprAccess 778850 1.57% 100.00% # Class of committed instruction |
| system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu0.commit.op_class_0::total 49613021 # Class of committed instruction |
| system.cpu0.commit.bw_lim_events 1780933 # number cycles where commit BW limit reached |
| system.cpu0.rob.rob_reads 169850432 # The number of ROB reads |
| system.cpu0.rob.rob_writes 120933247 # The number of ROB writes |
| system.cpu0.timesIdled 478916 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| system.cpu0.idleCycles 5546412 # Total number of cycles that the CPU has spent unscheduled due to idling |
| system.cpu0.quiesceCycles 3700805346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| system.cpu0.committedInsts 46729302 # Number of Instructions Simulated |
| system.cpu0.committedOps 46729302 # Number of Ops (including micro ops) Simulated |
| system.cpu0.cpi 2.557583 # CPI: Cycles Per Instruction |
| system.cpu0.cpi_total 2.557583 # CPI: Total CPI of All Threads |
| system.cpu0.ipc 0.390994 # IPC: Instructions Per Cycle |
| system.cpu0.ipc_total 0.390994 # IPC: Total IPC of All Threads |
| system.cpu0.int_regfile_reads 68048969 # number of integer regfile reads |
| system.cpu0.int_regfile_writes 37279666 # number of integer regfile writes |
| system.cpu0.fp_regfile_reads 121382 # number of floating regfile reads |
| system.cpu0.fp_regfile_writes 130068 # number of floating regfile writes |
| system.cpu0.misc_regfile_reads 1658488 # number of misc regfile reads |
| system.cpu0.misc_regfile_writes 782262 # number of misc regfile writes |
| system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.dcache.tags.replacements 1253915 # number of replacements |
| system.cpu0.dcache.tags.tagsinuse 506.032819 # Cycle average of tags in use |
| system.cpu0.dcache.tags.total_refs 10656048 # Total number of references to valid blocks. |
| system.cpu0.dcache.tags.sampled_refs 1254345 # Sample count of references to valid blocks. |
| system.cpu0.dcache.tags.avg_refs 8.495309 # Average number of references to valid blocks. |
| system.cpu0.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. |
| system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.032819 # Average occupied blocks per requestor |
| system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988345 # Average percentage of cache occupancy |
| system.cpu0.dcache.tags.occ_percent::total 0.988345 # Average percentage of cache occupancy |
| system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id |
| system.cpu0.dcache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id |
| system.cpu0.dcache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id |
| system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id |
| system.cpu0.dcache.tags.tag_accesses 56914873 # Number of tag accesses |
| system.cpu0.dcache.tags.data_accesses 56914873 # Number of data accesses |
| system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.dcache.ReadReq_hits::cpu0.data 6773563 # number of ReadReq hits |
| system.cpu0.dcache.ReadReq_hits::total 6773563 # number of ReadReq hits |
| system.cpu0.dcache.WriteReq_hits::cpu0.data 3523907 # number of WriteReq hits |
| system.cpu0.dcache.WriteReq_hits::total 3523907 # number of WriteReq hits |
| system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174492 # number of LoadLockedReq hits |
| system.cpu0.dcache.LoadLockedReq_hits::total 174492 # number of LoadLockedReq hits |
| system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179921 # number of StoreCondReq hits |
| system.cpu0.dcache.StoreCondReq_hits::total 179921 # number of StoreCondReq hits |
| system.cpu0.dcache.demand_hits::cpu0.data 10297470 # number of demand (read+write) hits |
| system.cpu0.dcache.demand_hits::total 10297470 # number of demand (read+write) hits |
| system.cpu0.dcache.overall_hits::cpu0.data 10297470 # number of overall hits |
| system.cpu0.dcache.overall_hits::total 10297470 # number of overall hits |
| system.cpu0.dcache.ReadReq_misses::cpu0.data 1555944 # number of ReadReq misses |
| system.cpu0.dcache.ReadReq_misses::total 1555944 # number of ReadReq misses |
| system.cpu0.dcache.WriteReq_misses::cpu0.data 1682220 # number of WriteReq misses |
| system.cpu0.dcache.WriteReq_misses::total 1682220 # number of WriteReq misses |
| system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19936 # number of LoadLockedReq misses |
| system.cpu0.dcache.LoadLockedReq_misses::total 19936 # number of LoadLockedReq misses |
| system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3029 # number of StoreCondReq misses |
| system.cpu0.dcache.StoreCondReq_misses::total 3029 # number of StoreCondReq misses |
| system.cpu0.dcache.demand_misses::cpu0.data 3238164 # number of demand (read+write) misses |
| system.cpu0.dcache.demand_misses::total 3238164 # number of demand (read+write) misses |
| system.cpu0.dcache.overall_misses::cpu0.data 3238164 # number of overall misses |
| system.cpu0.dcache.overall_misses::total 3238164 # number of overall misses |
| system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41483749500 # number of ReadReq miss cycles |
| system.cpu0.dcache.ReadReq_miss_latency::total 41483749500 # number of ReadReq miss cycles |
| system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85008982052 # number of WriteReq miss cycles |
| system.cpu0.dcache.WriteReq_miss_latency::total 85008982052 # number of WriteReq miss cycles |
| system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 398193000 # number of LoadLockedReq miss cycles |
| system.cpu0.dcache.LoadLockedReq_miss_latency::total 398193000 # number of LoadLockedReq miss cycles |
| system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17043500 # number of StoreCondReq miss cycles |
| system.cpu0.dcache.StoreCondReq_miss_latency::total 17043500 # number of StoreCondReq miss cycles |
| system.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552 # number of demand (read+write) miss cycles |
| system.cpu0.dcache.demand_miss_latency::total 126492731552 # number of demand (read+write) miss cycles |
| system.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552 # number of overall miss cycles |
| system.cpu0.dcache.overall_miss_latency::total 126492731552 # number of overall miss cycles |
| system.cpu0.dcache.ReadReq_accesses::cpu0.data 8329507 # number of ReadReq accesses(hits+misses) |
| system.cpu0.dcache.ReadReq_accesses::total 8329507 # number of ReadReq accesses(hits+misses) |
| system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206127 # number of WriteReq accesses(hits+misses) |
| system.cpu0.dcache.WriteReq_accesses::total 5206127 # number of WriteReq accesses(hits+misses) |
| system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194428 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu0.dcache.LoadLockedReq_accesses::total 194428 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182950 # number of StoreCondReq accesses(hits+misses) |
| system.cpu0.dcache.StoreCondReq_accesses::total 182950 # number of StoreCondReq accesses(hits+misses) |
| system.cpu0.dcache.demand_accesses::cpu0.data 13535634 # number of demand (read+write) accesses |
| system.cpu0.dcache.demand_accesses::total 13535634 # number of demand (read+write) accesses |
| system.cpu0.dcache.overall_accesses::cpu0.data 13535634 # number of overall (read+write) accesses |
| system.cpu0.dcache.overall_accesses::total 13535634 # number of overall (read+write) accesses |
| system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186799 # miss rate for ReadReq accesses |
| system.cpu0.dcache.ReadReq_miss_rate::total 0.186799 # miss rate for ReadReq accesses |
| system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323123 # miss rate for WriteReq accesses |
| system.cpu0.dcache.WriteReq_miss_rate::total 0.323123 # miss rate for WriteReq accesses |
| system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102537 # miss rate for LoadLockedReq accesses |
| system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102537 # miss rate for LoadLockedReq accesses |
| system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016556 # miss rate for StoreCondReq accesses |
| system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016556 # miss rate for StoreCondReq accesses |
| system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239233 # miss rate for demand accesses |
| system.cpu0.dcache.demand_miss_rate::total 0.239233 # miss rate for demand accesses |
| system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239233 # miss rate for overall accesses |
| system.cpu0.dcache.overall_miss_rate::total 0.239233 # miss rate for overall accesses |
| system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929 # average ReadReq miss latency |
| system.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929 # average ReadReq miss latency |
| system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737 # average WriteReq miss latency |
| system.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737 # average WriteReq miss latency |
| system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409 # average LoadLockedReq miss latency |
| system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409 # average LoadLockedReq miss latency |
| system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.774513 # average StoreCondReq miss latency |
| system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.774513 # average StoreCondReq miss latency |
| system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency |
| system.cpu0.dcache.demand_avg_miss_latency::total 39063.102286 # average overall miss latency |
| system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency |
| system.cpu0.dcache.overall_avg_miss_latency::total 39063.102286 # average overall miss latency |
| system.cpu0.dcache.blocked_cycles::no_mshrs 4473141 # number of cycles access was blocked |
| system.cpu0.dcache.blocked_cycles::no_targets 2637 # number of cycles access was blocked |
| system.cpu0.dcache.blocked::no_mshrs 108649 # number of cycles access was blocked |
| system.cpu0.dcache.blocked::no_targets 100 # number of cycles access was blocked |
| system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.170568 # average number of cycles each access was blocked |
| system.cpu0.dcache.avg_blocked_cycles::no_targets 26.370000 # average number of cycles each access was blocked |
| system.cpu0.dcache.writebacks::writebacks 737996 # number of writebacks |
| system.cpu0.dcache.writebacks::total 737996 # number of writebacks |
| system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 553324 # number of ReadReq MSHR hits |
| system.cpu0.dcache.ReadReq_mshr_hits::total 553324 # number of ReadReq MSHR hits |
| system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1430604 # number of WriteReq MSHR hits |
| system.cpu0.dcache.WriteReq_mshr_hits::total 1430604 # number of WriteReq MSHR hits |
| system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5325 # number of LoadLockedReq MSHR hits |
| system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5325 # number of LoadLockedReq MSHR hits |
| system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983928 # number of demand (read+write) MSHR hits |
| system.cpu0.dcache.demand_mshr_hits::total 1983928 # number of demand (read+write) MSHR hits |
| system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983928 # number of overall MSHR hits |
| system.cpu0.dcache.overall_mshr_hits::total 1983928 # number of overall MSHR hits |
| system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002620 # number of ReadReq MSHR misses |
| system.cpu0.dcache.ReadReq_mshr_misses::total 1002620 # number of ReadReq MSHR misses |
| system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251616 # number of WriteReq MSHR misses |
| system.cpu0.dcache.WriteReq_mshr_misses::total 251616 # number of WriteReq MSHR misses |
| system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14611 # number of LoadLockedReq MSHR misses |
| system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14611 # number of LoadLockedReq MSHR misses |
| system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3029 # number of StoreCondReq MSHR misses |
| system.cpu0.dcache.StoreCondReq_mshr_misses::total 3029 # number of StoreCondReq MSHR misses |
| system.cpu0.dcache.demand_mshr_misses::cpu0.data 1254236 # number of demand (read+write) MSHR misses |
| system.cpu0.dcache.demand_mshr_misses::total 1254236 # number of demand (read+write) MSHR misses |
| system.cpu0.dcache.overall_mshr_misses::cpu0.data 1254236 # number of overall MSHR misses |
| system.cpu0.dcache.overall_mshr_misses::total 1254236 # number of overall MSHR misses |
| system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable |
| system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable |
| system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable |
| system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9909 # number of WriteReq MSHR uncacheable |
| system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses |
| system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16886 # number of overall MSHR uncacheable misses |
| system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31595131000 # number of ReadReq MSHR miss cycles |
| system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31595131000 # number of ReadReq MSHR miss cycles |
| system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13207477923 # number of WriteReq MSHR miss cycles |
| system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13207477923 # number of WriteReq MSHR miss cycles |
| system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 169739500 # number of LoadLockedReq MSHR miss cycles |
| system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 169739500 # number of LoadLockedReq MSHR miss cycles |
| system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14014500 # number of StoreCondReq MSHR miss cycles |
| system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14014500 # number of StoreCondReq MSHR miss cycles |
| system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44802608923 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.dcache.demand_mshr_miss_latency::total 44802608923 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44802608923 # number of overall MSHR miss cycles |
| system.cpu0.dcache.overall_mshr_miss_latency::total 44802608923 # number of overall MSHR miss cycles |
| system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557264500 # number of ReadReq MSHR uncacheable cycles |
| system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557264500 # number of ReadReq MSHR uncacheable cycles |
| system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557264500 # number of overall MSHR uncacheable cycles |
| system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557264500 # number of overall MSHR uncacheable cycles |
| system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120370 # mshr miss rate for ReadReq accesses |
| system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses |
| system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048331 # mshr miss rate for WriteReq accesses |
| system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048331 # mshr miss rate for WriteReq accesses |
| system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075149 # mshr miss rate for LoadLockedReq accesses |
| system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075149 # mshr miss rate for LoadLockedReq accesses |
| system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016556 # mshr miss rate for StoreCondReq accesses |
| system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016556 # mshr miss rate for StoreCondReq accesses |
| system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for demand accesses |
| system.cpu0.dcache.demand_mshr_miss_rate::total 0.092662 # mshr miss rate for demand accesses |
| system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for overall accesses |
| system.cpu0.dcache.overall_mshr_miss_rate::total 0.092662 # mshr miss rate for overall accesses |
| system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072 # average ReadReq mshr miss latency |
| system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072 # average ReadReq mshr miss latency |
| system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374 # average WriteReq mshr miss latency |
| system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374 # average WriteReq mshr miss latency |
| system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435 # average LoadLockedReq mshr miss latency |
| system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435 # average LoadLockedReq mshr miss latency |
| system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.774513 # average StoreCondReq mshr miss latency |
| system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.774513 # average StoreCondReq mshr miss latency |
| system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency |
| system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency |
| system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency |
| system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency |
| system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677 # average ReadReq mshr uncacheable latency |
| system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677 # average ReadReq mshr uncacheable latency |
| system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512 # average overall mshr uncacheable latency |
| system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512 # average overall mshr uncacheable latency |
| system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.icache.tags.replacements 891919 # number of replacements |
| system.cpu0.icache.tags.tagsinuse 509.368701 # Cycle average of tags in use |
| system.cpu0.icache.tags.total_refs 7561136 # Total number of references to valid blocks. |
| system.cpu0.icache.tags.sampled_refs 892430 # Sample count of references to valid blocks. |
| system.cpu0.icache.tags.avg_refs 8.472526 # Average number of references to valid blocks. |
| system.cpu0.icache.tags.warmup_cycle 30335024500 # Cycle when the warmup percentage was hit. |
| system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.368701 # Average occupied blocks per requestor |
| system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994861 # Average percentage of cache occupancy |
| system.cpu0.icache.tags.occ_percent::total 0.994861 # Average percentage of cache occupancy |
| system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id |
| system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id |
| system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| system.cpu0.icache.tags.tag_accesses 9401165 # Number of tag accesses |
| system.cpu0.icache.tags.data_accesses 9401165 # Number of data accesses |
| system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.icache.ReadReq_hits::cpu0.inst 7561136 # number of ReadReq hits |
| system.cpu0.icache.ReadReq_hits::total 7561136 # number of ReadReq hits |
| system.cpu0.icache.demand_hits::cpu0.inst 7561136 # number of demand (read+write) hits |
| system.cpu0.icache.demand_hits::total 7561136 # number of demand (read+write) hits |
| system.cpu0.icache.overall_hits::cpu0.inst 7561136 # number of overall hits |
| system.cpu0.icache.overall_hits::total 7561136 # number of overall hits |
| system.cpu0.icache.ReadReq_misses::cpu0.inst 947367 # number of ReadReq misses |
| system.cpu0.icache.ReadReq_misses::total 947367 # number of ReadReq misses |
| system.cpu0.icache.demand_misses::cpu0.inst 947367 # number of demand (read+write) misses |
| system.cpu0.icache.demand_misses::total 947367 # number of demand (read+write) misses |
| system.cpu0.icache.overall_misses::cpu0.inst 947367 # number of overall misses |
| system.cpu0.icache.overall_misses::total 947367 # number of overall misses |
| system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858743493 # number of ReadReq miss cycles |
| system.cpu0.icache.ReadReq_miss_latency::total 13858743493 # number of ReadReq miss cycles |
| system.cpu0.icache.demand_miss_latency::cpu0.inst 13858743493 # number of demand (read+write) miss cycles |
| system.cpu0.icache.demand_miss_latency::total 13858743493 # number of demand (read+write) miss cycles |
| system.cpu0.icache.overall_miss_latency::cpu0.inst 13858743493 # number of overall miss cycles |
| system.cpu0.icache.overall_miss_latency::total 13858743493 # number of overall miss cycles |
| system.cpu0.icache.ReadReq_accesses::cpu0.inst 8508503 # number of ReadReq accesses(hits+misses) |
| system.cpu0.icache.ReadReq_accesses::total 8508503 # number of ReadReq accesses(hits+misses) |
| system.cpu0.icache.demand_accesses::cpu0.inst 8508503 # number of demand (read+write) accesses |
| system.cpu0.icache.demand_accesses::total 8508503 # number of demand (read+write) accesses |
| system.cpu0.icache.overall_accesses::cpu0.inst 8508503 # number of overall (read+write) accesses |
| system.cpu0.icache.overall_accesses::total 8508503 # number of overall (read+write) accesses |
| system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111344 # miss rate for ReadReq accesses |
| system.cpu0.icache.ReadReq_miss_rate::total 0.111344 # miss rate for ReadReq accesses |
| system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111344 # miss rate for demand accesses |
| system.cpu0.icache.demand_miss_rate::total 0.111344 # miss rate for demand accesses |
| system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111344 # miss rate for overall accesses |
| system.cpu0.icache.overall_miss_rate::total 0.111344 # miss rate for overall accesses |
| system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630 # average ReadReq miss latency |
| system.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630 # average ReadReq miss latency |
| system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency |
| system.cpu0.icache.demand_avg_miss_latency::total 14628.695630 # average overall miss latency |
| system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency |
| system.cpu0.icache.overall_avg_miss_latency::total 14628.695630 # average overall miss latency |
| system.cpu0.icache.blocked_cycles::no_mshrs 7760 # number of cycles access was blocked |
| system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu0.icache.blocked::no_mshrs 263 # number of cycles access was blocked |
| system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.505703 # average number of cycles each access was blocked |
| system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu0.icache.writebacks::writebacks 891919 # number of writebacks |
| system.cpu0.icache.writebacks::total 891919 # number of writebacks |
| system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54705 # number of ReadReq MSHR hits |
| system.cpu0.icache.ReadReq_mshr_hits::total 54705 # number of ReadReq MSHR hits |
| system.cpu0.icache.demand_mshr_hits::cpu0.inst 54705 # number of demand (read+write) MSHR hits |
| system.cpu0.icache.demand_mshr_hits::total 54705 # number of demand (read+write) MSHR hits |
| system.cpu0.icache.overall_mshr_hits::cpu0.inst 54705 # number of overall MSHR hits |
| system.cpu0.icache.overall_mshr_hits::total 54705 # number of overall MSHR hits |
| system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 892662 # number of ReadReq MSHR misses |
| system.cpu0.icache.ReadReq_mshr_misses::total 892662 # number of ReadReq MSHR misses |
| system.cpu0.icache.demand_mshr_misses::cpu0.inst 892662 # number of demand (read+write) MSHR misses |
| system.cpu0.icache.demand_mshr_misses::total 892662 # number of demand (read+write) MSHR misses |
| system.cpu0.icache.overall_mshr_misses::cpu0.inst 892662 # number of overall MSHR misses |
| system.cpu0.icache.overall_mshr_misses::total 892662 # number of overall MSHR misses |
| system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12247880494 # number of ReadReq MSHR miss cycles |
| system.cpu0.icache.ReadReq_mshr_miss_latency::total 12247880494 # number of ReadReq MSHR miss cycles |
| system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12247880494 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.icache.demand_mshr_miss_latency::total 12247880494 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12247880494 # number of overall MSHR miss cycles |
| system.cpu0.icache.overall_mshr_miss_latency::total 12247880494 # number of overall MSHR miss cycles |
| system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for ReadReq accesses |
| system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104914 # mshr miss rate for ReadReq accesses |
| system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for demand accesses |
| system.cpu0.icache.demand_mshr_miss_rate::total 0.104914 # mshr miss rate for demand accesses |
| system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for overall accesses |
| system.cpu0.icache.overall_mshr_miss_rate::total 0.104914 # mshr miss rate for overall accesses |
| system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average ReadReq mshr miss latency |
| system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933 # average ReadReq mshr miss latency |
| system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency |
| system.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency |
| system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency |
| system.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency |
| system.cpu1.branchPred.lookups 4440494 # Number of BP lookups |
| system.cpu1.branchPred.condPredicted 3820633 # Number of conditional branches predicted |
| system.cpu1.branchPred.condIncorrect 114977 # Number of conditional branches incorrect |
| system.cpu1.branchPred.BTBLookups 2284731 # Number of BTB lookups |
| system.cpu1.branchPred.BTBHits 882766 # Number of BTB hits |
| system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu1.branchPred.BTBHitPct 38.637634 # BTB Hit Percentage |
| system.cpu1.branchPred.usedRAS 229523 # Number of times the RAS was used to get a target. |
| system.cpu1.branchPred.RASInCorrect 8540 # Number of incorrect RAS predictions. |
| system.cpu1.branchPred.indirectLookups 1232926 # Number of indirect predictor lookups. |
| system.cpu1.branchPred.indirectHits 164040 # Number of indirect target hits. |
| system.cpu1.branchPred.indirectMisses 1068886 # Number of indirect misses. |
| system.cpu1.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. |
| system.cpu1.dtb.fetch_hits 0 # ITB hits |
| system.cpu1.dtb.fetch_misses 0 # ITB misses |
| system.cpu1.dtb.fetch_acv 0 # ITB acv |
| system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| system.cpu1.dtb.read_hits 2425125 # DTB read hits |
| system.cpu1.dtb.read_misses 16040 # DTB read misses |
| system.cpu1.dtb.read_acv 82 # DTB read access violations |
| system.cpu1.dtb.read_accesses 432289 # DTB read accesses |
| system.cpu1.dtb.write_hits 1438640 # DTB write hits |
| system.cpu1.dtb.write_misses 3531 # DTB write misses |
| system.cpu1.dtb.write_acv 65 # DTB write access violations |
| system.cpu1.dtb.write_accesses 162605 # DTB write accesses |
| system.cpu1.dtb.data_hits 3863765 # DTB hits |
| system.cpu1.dtb.data_misses 19571 # DTB misses |
| system.cpu1.dtb.data_acv 147 # DTB access violations |
| system.cpu1.dtb.data_accesses 594894 # DTB accesses |
| system.cpu1.itb.fetch_hits 679335 # ITB hits |
| system.cpu1.itb.fetch_misses 3486 # ITB misses |
| system.cpu1.itb.fetch_acv 144 # ITB acv |
| system.cpu1.itb.fetch_accesses 682821 # ITB accesses |
| system.cpu1.itb.read_hits 0 # DTB read hits |
| system.cpu1.itb.read_misses 0 # DTB read misses |
| system.cpu1.itb.read_acv 0 # DTB read access violations |
| system.cpu1.itb.read_accesses 0 # DTB read accesses |
| system.cpu1.itb.write_hits 0 # DTB write hits |
| system.cpu1.itb.write_misses 0 # DTB write misses |
| system.cpu1.itb.write_acv 0 # DTB write access violations |
| system.cpu1.itb.write_accesses 0 # DTB write accesses |
| system.cpu1.itb.data_hits 0 # DTB hits |
| system.cpu1.itb.data_misses 0 # DTB misses |
| system.cpu1.itb.data_acv 0 # DTB access violations |
| system.cpu1.itb.data_accesses 0 # DTB accesses |
| system.cpu1.numPwrStateTransitions 5088 # Number of power state transitions |
| system.cpu1.pwrStateClkGateDist::samples 2544 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::mean 747516916.077044 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::stdev 396242813.132808 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::1000-5e+10 2544 100.00% 100.00% # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::max_value 975504000 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateClkGateDist::total 2544 # Distribution of time spent in the clock gated state |
| system.cpu1.pwrStateResidencyTicks::ON 8774063000 # Cumulative time (in ticks) in various power states |
| system.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500 # Cumulative time (in ticks) in various power states |
| system.cpu1.numCycles 17550671 # number of cpu cycles simulated |
| system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu1.fetch.icacheStallCycles 7093737 # Number of cycles fetch is stalled on an Icache miss |
| system.cpu1.fetch.Insts 17628277 # Number of instructions fetch has processed |
| system.cpu1.fetch.Branches 4440494 # Number of branches that fetch encountered |
| system.cpu1.fetch.predictedBranches 1276329 # Number of branches that fetch has predicted taken |
| system.cpu1.fetch.Cycles 9234250 # Number of cycles fetch has run and was not squashing or blocked |
| system.cpu1.fetch.SquashCycles 381282 # Number of cycles fetch has spent squashing |
| system.cpu1.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb |
| system.cpu1.fetch.MiscStallCycles 26389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| system.cpu1.fetch.PendingTrapStallCycles 68063 # Number of stall cycles due to pending traps |
| system.cpu1.fetch.PendingQuiesceStallCycles 51076 # Number of stall cycles due to pending quiesce instructions |
| system.cpu1.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR |
| system.cpu1.fetch.CacheLines 1982953 # Number of cache lines fetched |
| system.cpu1.fetch.IcacheSquashes 84304 # Number of outstanding Icache misses that were squashed |
| system.cpu1.fetch.rateDist::samples 16664213 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::mean 1.057852 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::stdev 2.464693 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::0 13566532 81.41% 81.41% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::1 196080 1.18% 82.59% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::2 329765 1.98% 84.57% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::3 235529 1.41% 85.98% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::4 402874 2.42% 88.40% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::5 150126 0.90% 89.30% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::6 175137 1.05% 90.35% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::7 212228 1.27% 91.62% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::8 1395942 8.38% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.rateDist::total 16664213 # Number of instructions fetched each cycle (Total) |
| system.cpu1.fetch.branchRate 0.253010 # Number of branch fetches per cycle |
| system.cpu1.fetch.rate 1.004422 # Number of inst fetches per cycle |
| system.cpu1.decode.IdleCycles 5803889 # Number of cycles decode is idle |
| system.cpu1.decode.BlockedCycles 8198941 # Number of cycles decode is blocked |
| system.cpu1.decode.RunCycles 2195429 # Number of cycles decode is running |
| system.cpu1.decode.UnblockCycles 282754 # Number of cycles decode is unblocking |
| system.cpu1.decode.SquashCycles 183199 # Number of cycles decode is squashing |
| system.cpu1.decode.BranchResolved 845965 # Number of times decode resolved a branch |
| system.cpu1.decode.BranchMispred 7619 # Number of times decode detected a branch misprediction |
| system.cpu1.decode.DecodedInsts 14397519 # Number of instructions handled by decode |
| system.cpu1.decode.SquashedInsts 23764 # Number of squashed instructions handled by decode |
| system.cpu1.rename.SquashCycles 183199 # Number of cycles rename is squashing |
| system.cpu1.rename.IdleCycles 5993501 # Number of cycles rename is idle |
| system.cpu1.rename.BlockCycles 917111 # Number of cycles rename is blocking |
| system.cpu1.rename.serializeStallCycles 6016357 # count of cycles rename stalled for serializing inst |
| system.cpu1.rename.RunCycles 2289218 # Number of cycles rename is running |
| system.cpu1.rename.UnblockCycles 1264825 # Number of cycles rename is unblocking |
| system.cpu1.rename.RenamedInsts 13624374 # Number of instructions processed by rename |
| system.cpu1.rename.ROBFullEvents 3775 # Number of times rename has blocked due to ROB full |
| system.cpu1.rename.IQFullEvents 108540 # Number of times rename has blocked due to IQ full |
| system.cpu1.rename.LQFullEvents 34178 # Number of times rename has blocked due to LQ full |
| system.cpu1.rename.SQFullEvents 643759 # Number of times rename has blocked due to SQ full |
| system.cpu1.rename.RenamedOperands 9046149 # Number of destination operands rename has renamed |
| system.cpu1.rename.RenameLookups 16244839 # Number of register rename lookups that rename has made |
| system.cpu1.rename.int_rename_lookups 16178929 # Number of integer rename lookups |
| system.cpu1.rename.fp_rename_lookups 59321 # Number of floating rename lookups |
| system.cpu1.rename.CommittedMaps 7078981 # Number of HB maps that are committed |
| system.cpu1.rename.UndoneMaps 1967160 # Number of HB maps that are undone due to squashing |
| system.cpu1.rename.serializingInsts 511491 # count of serializing insts renamed |
| system.cpu1.rename.tempSerializingInsts 53621 # count of temporary serializing insts renamed |
| system.cpu1.rename.skidInsts 2283119 # count of insts added to the skid buffer |
| system.cpu1.memDep0.insertedLoads 2539964 # Number of loads inserted to the mem dependence unit. |
| system.cpu1.memDep0.insertedStores 1543921 # Number of stores inserted to the mem dependence unit. |
| system.cpu1.memDep0.conflictingLoads 323106 # Number of conflicting loads. |
| system.cpu1.memDep0.conflictingStores 168966 # Number of conflicting stores. |
| system.cpu1.iq.iqInstsAdded 11939663 # Number of instructions added to the IQ (excludes non-spec) |
| system.cpu1.iq.iqNonSpecInstsAdded 585885 # Number of non-speculative instructions added to the IQ |
| system.cpu1.iq.iqInstsIssued 11455956 # Number of instructions issued |
| system.cpu1.iq.iqSquashedInstsIssued 28942 # Number of squashed instructions issued |
| system.cpu1.iq.iqSquashedInstsExamined 2572399 # Number of squashed instructions iterated over during squash; mainly for profiling |
| system.cpu1.iq.iqSquashedOperandsExamined 1228155 # Number of squashed operands that are examined and possibly removed from graph |
| system.cpu1.iq.iqSquashedNonSpecRemoved 432246 # Number of squashed non-spec instructions that were removed |
| system.cpu1.iq.issued_per_cycle::samples 16664213 # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::mean 0.687459 # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::stdev 1.414504 # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::0 11970475 71.83% 71.83% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::1 2021121 12.13% 83.96% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::2 863574 5.18% 89.14% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::3 618225 3.71% 92.85% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::4 572472 3.44% 96.29% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::5 300775 1.80% 98.09% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::6 197233 1.18% 99.28% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::7 86853 0.52% 99.80% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::8 33485 0.20% 100.00% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| system.cpu1.iq.issued_per_cycle::total 16664213 # Number of insts issued each cycle |
| system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::IntAlu 33486 10.24% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.24% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::MemRead 173880 53.16% 63.40% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::MemWrite 104341 31.90% 95.30% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatMemRead 7997 2.44% 97.75% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::FloatMemWrite 7375 2.25% 100.00% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu1.iq.FU_type_0::No_OpClass 4756 0.04% 0.04% # Type of FU issued |
| system.cpu1.iq.FU_type_0::IntAlu 7097834 61.96% 62.00% # Type of FU issued |
| system.cpu1.iq.FU_type_0::IntMult 17086 0.15% 62.15% # Type of FU issued |
| system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.27% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.27% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.29% # Type of FU issued |
| system.cpu1.iq.FU_type_0::MemRead 2506692 21.88% 84.17% # Type of FU issued |
| system.cpu1.iq.FU_type_0::MemWrite 1424790 12.44% 96.61% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatMemRead 45041 0.39% 97.00% # Type of FU issued |
| system.cpu1.iq.FU_type_0::FloatMemWrite 43535 0.38% 97.38% # Type of FU issued |
| system.cpu1.iq.FU_type_0::IprAccess 299845 2.62% 100.00% # Type of FU issued |
| system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| system.cpu1.iq.FU_type_0::total 11455956 # Type of FU issued |
| system.cpu1.iq.rate 0.652736 # Inst issue rate |
| system.cpu1.iq.fu_busy_cnt 327079 # FU busy when requested |
| system.cpu1.iq.fu_busy_rate 0.028551 # FU busy rate (busy events/executed inst) |
| system.cpu1.iq.int_inst_queue_reads 39706848 # Number of integer instruction queue reads |
| system.cpu1.iq.int_inst_queue_writes 14995495 # Number of integer instruction queue writes |
| system.cpu1.iq.int_inst_queue_wakeup_accesses 10932885 # Number of integer instruction queue wakeup accesses |
| system.cpu1.iq.fp_inst_queue_reads 225297 # Number of floating instruction queue reads |
| system.cpu1.iq.fp_inst_queue_writes 107483 # Number of floating instruction queue writes |
| system.cpu1.iq.fp_inst_queue_wakeup_accesses 104737 # Number of floating instruction queue wakeup accesses |
| system.cpu1.iq.int_alu_accesses 11657954 # Number of integer alu accesses |
| system.cpu1.iq.fp_alu_accesses 120325 # Number of floating point alu accesses |
| system.cpu1.iew.lsq.thread0.forwLoads 118525 # Number of loads that had data forwarded from stores |
| system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| system.cpu1.iew.lsq.thread0.squashedLoads 552207 # Number of loads squashed |
| system.cpu1.iew.lsq.thread0.ignoredResponses 1214 # Number of memory responses ignored because the instruction is squashed |
| system.cpu1.iew.lsq.thread0.memOrderViolation 5210 # Number of memory ordering violations |
| system.cpu1.iew.lsq.thread0.squashedStores 179004 # Number of stores squashed |
| system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| system.cpu1.iew.lsq.thread0.rescheduledLoads 539 # Number of loads that were rescheduled |
| system.cpu1.iew.lsq.thread0.cacheBlocked 99906 # Number of times an access to memory failed due to the cache being blocked |
| system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| system.cpu1.iew.iewSquashCycles 183199 # Number of cycles IEW is squashing |
| system.cpu1.iew.iewBlockCycles 564470 # Number of cycles IEW is blocking |
| system.cpu1.iew.iewUnblockCycles 284501 # Number of cycles IEW is unblocking |
| system.cpu1.iew.iewDispatchedInsts 13175740 # Number of instructions dispatched to IQ |
| system.cpu1.iew.iewDispSquashedInsts 58730 # Number of squashed instructions skipped by dispatch |
| system.cpu1.iew.iewDispLoadInsts 2539964 # Number of dispatched load instructions |
| system.cpu1.iew.iewDispStoreInsts 1543921 # Number of dispatched store instructions |
| system.cpu1.iew.iewDispNonSpecInsts 532175 # Number of dispatched non-speculative instructions |
| system.cpu1.iew.iewIQFullEvents 7107 # Number of times the IQ has become full, causing a stall |
| system.cpu1.iew.iewLSQFullEvents 276039 # Number of times the LSQ has become full, causing a stall |
| system.cpu1.iew.memOrderViolationEvents 5210 # Number of memory order violations |
| system.cpu1.iew.predictedTakenIncorrect 46730 # Number of branches that were predicted taken incorrectly |
| system.cpu1.iew.predictedNotTakenIncorrect 149015 # Number of branches that were predicted not taken incorrectly |
| system.cpu1.iew.branchMispredicts 195745 # Number of branch mispredicts detected at execute |
| system.cpu1.iew.iewExecutedInsts 11262138 # Number of executed instructions |
| system.cpu1.iew.iewExecLoadInsts 2450359 # Number of load instructions executed |
| system.cpu1.iew.iewExecSquashedInsts 193817 # Number of squashed instructions skipped in execute |
| system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| system.cpu1.iew.exec_nop 650192 # number of nop insts executed |
| system.cpu1.iew.exec_refs 3899095 # number of memory reference insts executed |
| system.cpu1.iew.exec_branches 1684701 # Number of branches executed |
| system.cpu1.iew.exec_stores 1448736 # Number of stores executed |
| system.cpu1.iew.exec_rate 0.641693 # Inst execution rate |
| system.cpu1.iew.wb_sent 11092333 # cumulative count of insts sent to commit |
| system.cpu1.iew.wb_count 11037622 # cumulative count of insts written-back |
| system.cpu1.iew.wb_producers 5277529 # num instructions producing a value |
| system.cpu1.iew.wb_consumers 7434192 # num instructions consuming a value |
| system.cpu1.iew.wb_rate 0.628900 # insts written-back per cycle |
| system.cpu1.iew.wb_fanout 0.709899 # average fanout of values written-back |
| system.cpu1.commit.commitSquashedInsts 2589103 # The number of squashed insts skipped by commit |
| system.cpu1.commit.commitNonSpecStalls 153639 # The number of times commit has been forced to stall to communicate backwards |
| system.cpu1.commit.branchMispredicts 170452 # The number of times a branch was mispredicted |
| system.cpu1.commit.committed_per_cycle::samples 16200161 # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::mean 0.644352 # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::stdev 1.619659 # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::0 12420478 76.67% 76.67% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::1 1746852 10.78% 87.45% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::2 623239 3.85% 91.30% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::3 386399 2.39% 93.68% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::4 294857 1.82% 95.50% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::5 125210 0.77% 96.28% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::6 112311 0.69% 96.97% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::7 119786 0.74% 97.71% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::8 371029 2.29% 100.00% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| system.cpu1.commit.committed_per_cycle::total 16200161 # Number of insts commited each cycle |
| system.cpu1.commit.committedInsts 10438605 # Number of instructions committed |
| system.cpu1.commit.committedOps 10438605 # Number of ops (including micro ops) committed |
| system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| system.cpu1.commit.refs 3352674 # Number of memory references committed |
| system.cpu1.commit.loads 1987757 # Number of loads committed |
| system.cpu1.commit.membars 48909 # Number of memory barriers committed |
| system.cpu1.commit.branches 1497531 # Number of branches committed |
| system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. |
| system.cpu1.commit.int_insts 9696003 # Number of committed integer instructions. |
| system.cpu1.commit.function_calls 163829 # Number of function calls committed. |
| system.cpu1.commit.op_class_0::No_OpClass 490211 4.70% 4.70% # Class of committed instruction |
| system.cpu1.commit.op_class_0::IntAlu 6213226 59.52% 64.22% # Class of committed instruction |
| system.cpu1.commit.op_class_0::IntMult 16788 0.16% 64.38% # Class of committed instruction |
| system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.51% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.51% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.54% # Class of committed instruction |
| system.cpu1.commit.op_class_0::MemRead 1991924 19.08% 83.62% # Class of committed instruction |
| system.cpu1.commit.op_class_0::MemWrite 1323832 12.68% 96.30% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction |
| system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction |
| system.cpu1.commit.op_class_0::IprAccess 299845 2.87% 100.00% # Class of committed instruction |
| system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu1.commit.op_class_0::total 10438605 # Class of committed instruction |
| system.cpu1.commit.bw_lim_events 371029 # number cycles where commit BW limit reached |
| system.cpu1.rob.rob_reads 28746473 # The number of ROB reads |
| system.cpu1.rob.rob_writes 26517839 # The number of ROB writes |
| system.cpu1.timesIdled 134718 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| system.cpu1.idleCycles 886458 # Total number of cycles that the CPU has spent unscheduled due to idling |
| system.cpu1.quiesceCycles 3803363525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| system.cpu1.committedInsts 9953144 # Number of Instructions Simulated |
| system.cpu1.committedOps 9953144 # Number of Ops (including micro ops) Simulated |
| system.cpu1.cpi 1.763329 # CPI: Cycles Per Instruction |
| system.cpu1.cpi_total 1.763329 # CPI: Total CPI of All Threads |
| system.cpu1.ipc 0.567109 # IPC: Instructions Per Cycle |
| system.cpu1.ipc_total 0.567109 # IPC: Total IPC of All Threads |
| system.cpu1.int_regfile_reads 14490611 # number of integer regfile reads |
| system.cpu1.int_regfile_writes 7893529 # number of integer regfile writes |
| system.cpu1.fp_regfile_reads 58631 # number of floating regfile reads |
| system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes |
| system.cpu1.misc_regfile_reads 573327 # number of misc regfile reads |
| system.cpu1.misc_regfile_writes 245000 # number of misc regfile writes |
| system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu1.dcache.tags.replacements 130880 # number of replacements |
| system.cpu1.dcache.tags.tagsinuse 488.755319 # Cycle average of tags in use |
| system.cpu1.dcache.tags.total_refs 3056587 # Total number of references to valid blocks. |
| system.cpu1.dcache.tags.sampled_refs 131392 # Sample count of references to valid blocks. |
| system.cpu1.dcache.tags.avg_refs 23.263113 # Average number of references to valid blocks. |
| system.cpu1.dcache.tags.warmup_cycle 49534102500 # Cycle when the warmup percentage was hit. |
| system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.755319 # Average occupied blocks per requestor |
| system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954600 # Average percentage of cache occupancy |
| system.cpu1.dcache.tags.occ_percent::total 0.954600 # Average percentage of cache occupancy |
| system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id |
| system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu1.dcache.tags.tag_accesses 14487576 # Number of tag accesses |
| system.cpu1.dcache.tags.data_accesses 14487576 # Number of data accesses |
| system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu1.dcache.ReadReq_hits::cpu1.data 1941589 # number of ReadReq hits |
| system.cpu1.dcache.ReadReq_hits::total 1941589 # number of ReadReq hits |
| system.cpu1.dcache.WriteReq_hits::cpu1.data 1026269 # number of WriteReq hits |
| system.cpu1.dcache.WriteReq_hits::total 1026269 # number of WriteReq hits |
| system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40594 # number of LoadLockedReq hits |
| system.cpu1.dcache.LoadLockedReq_hits::total 40594 # number of LoadLockedReq hits |
| system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37239 # number of StoreCondReq hits |
| system.cpu1.dcache.StoreCondReq_hits::total 37239 # number of StoreCondReq hits |
| system.cpu1.dcache.demand_hits::cpu1.data 2967858 # number of demand (read+write) hits |
| system.cpu1.dcache.demand_hits::total 2967858 # number of demand (read+write) hits |
| system.cpu1.dcache.overall_hits::cpu1.data 2967858 # number of overall hits |
| system.cpu1.dcache.overall_hits::total 2967858 # number of overall hits |
| system.cpu1.dcache.ReadReq_misses::cpu1.data 240679 # number of ReadReq misses |
| system.cpu1.dcache.ReadReq_misses::total 240679 # number of ReadReq misses |
| system.cpu1.dcache.WriteReq_misses::cpu1.data 291916 # number of WriteReq misses |
| system.cpu1.dcache.WriteReq_misses::total 291916 # number of WriteReq misses |
| system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5260 # number of LoadLockedReq misses |
| system.cpu1.dcache.LoadLockedReq_misses::total 5260 # number of LoadLockedReq misses |
| system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3088 # number of StoreCondReq misses |
| system.cpu1.dcache.StoreCondReq_misses::total 3088 # number of StoreCondReq misses |
| system.cpu1.dcache.demand_misses::cpu1.data 532595 # number of demand (read+write) misses |
| system.cpu1.dcache.demand_misses::total 532595 # number of demand (read+write) misses |
| system.cpu1.dcache.overall_misses::cpu1.data 532595 # number of overall misses |
| system.cpu1.dcache.overall_misses::total 532595 # number of overall misses |
| system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3354943500 # number of ReadReq miss cycles |
| system.cpu1.dcache.ReadReq_miss_latency::total 3354943500 # number of ReadReq miss cycles |
| system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12208160588 # number of WriteReq miss cycles |
| system.cpu1.dcache.WriteReq_miss_latency::total 12208160588 # number of WriteReq miss cycles |
| system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 53604000 # number of LoadLockedReq miss cycles |
| system.cpu1.dcache.LoadLockedReq_miss_latency::total 53604000 # number of LoadLockedReq miss cycles |
| system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17137500 # number of StoreCondReq miss cycles |
| system.cpu1.dcache.StoreCondReq_miss_latency::total 17137500 # number of StoreCondReq miss cycles |
| system.cpu1.dcache.demand_miss_latency::cpu1.data 15563104088 # number of demand (read+write) miss cycles |
| system.cpu1.dcache.demand_miss_latency::total 15563104088 # number of demand (read+write) miss cycles |
| system.cpu1.dcache.overall_miss_latency::cpu1.data 15563104088 # number of overall miss cycles |
| system.cpu1.dcache.overall_miss_latency::total 15563104088 # number of overall miss cycles |
| system.cpu1.dcache.ReadReq_accesses::cpu1.data 2182268 # number of ReadReq accesses(hits+misses) |
| system.cpu1.dcache.ReadReq_accesses::total 2182268 # number of ReadReq accesses(hits+misses) |
| system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318185 # number of WriteReq accesses(hits+misses) |
| system.cpu1.dcache.WriteReq_accesses::total 1318185 # number of WriteReq accesses(hits+misses) |
| system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45854 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu1.dcache.LoadLockedReq_accesses::total 45854 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40327 # number of StoreCondReq accesses(hits+misses) |
| system.cpu1.dcache.StoreCondReq_accesses::total 40327 # number of StoreCondReq accesses(hits+misses) |
| system.cpu1.dcache.demand_accesses::cpu1.data 3500453 # number of demand (read+write) accesses |
| system.cpu1.dcache.demand_accesses::total 3500453 # number of demand (read+write) accesses |
| system.cpu1.dcache.overall_accesses::cpu1.data 3500453 # number of overall (read+write) accesses |
| system.cpu1.dcache.overall_accesses::total 3500453 # number of overall (read+write) accesses |
| system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110288 # miss rate for ReadReq accesses |
| system.cpu1.dcache.ReadReq_miss_rate::total 0.110288 # miss rate for ReadReq accesses |
| system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221453 # miss rate for WriteReq accesses |
| system.cpu1.dcache.WriteReq_miss_rate::total 0.221453 # miss rate for WriteReq accesses |
| system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.114712 # miss rate for LoadLockedReq accesses |
| system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.114712 # miss rate for LoadLockedReq accesses |
| system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076574 # miss rate for StoreCondReq accesses |
| system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076574 # miss rate for StoreCondReq accesses |
| system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152150 # miss rate for demand accesses |
| system.cpu1.dcache.demand_miss_rate::total 0.152150 # miss rate for demand accesses |
| system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152150 # miss rate for overall accesses |
| system.cpu1.dcache.overall_miss_rate::total 0.152150 # miss rate for overall accesses |
| system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098 # average ReadReq miss latency |
| system.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098 # average ReadReq miss latency |
| system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778 # average WriteReq miss latency |
| system.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778 # average WriteReq miss latency |
| system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525 # average LoadLockedReq miss latency |
| system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525 # average LoadLockedReq miss latency |
| system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5549.708549 # average StoreCondReq miss latency |
| system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5549.708549 # average StoreCondReq miss latency |
| system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency |
| system.cpu1.dcache.demand_avg_miss_latency::total 29221.273365 # average overall miss latency |
| system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency |
| system.cpu1.dcache.overall_avg_miss_latency::total 29221.273365 # average overall miss latency |
| system.cpu1.dcache.blocked_cycles::no_mshrs 720106 # number of cycles access was blocked |
| system.cpu1.dcache.blocked_cycles::no_targets 464 # number of cycles access was blocked |
| system.cpu1.dcache.blocked::no_mshrs 24866 # number of cycles access was blocked |
| system.cpu1.dcache.blocked::no_targets 14 # number of cycles access was blocked |
| system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.959463 # average number of cycles each access was blocked |
| system.cpu1.dcache.avg_blocked_cycles::no_targets 33.142857 # average number of cycles each access was blocked |
| system.cpu1.dcache.writebacks::writebacks 84401 # number of writebacks |
| system.cpu1.dcache.writebacks::total 84401 # number of writebacks |
| system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147677 # number of ReadReq MSHR hits |
| system.cpu1.dcache.ReadReq_mshr_hits::total 147677 # number of ReadReq MSHR hits |
| system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243516 # number of WriteReq MSHR hits |
| system.cpu1.dcache.WriteReq_mshr_hits::total 243516 # number of WriteReq MSHR hits |
| system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 792 # number of LoadLockedReq MSHR hits |
| system.cpu1.dcache.LoadLockedReq_mshr_hits::total 792 # number of LoadLockedReq MSHR hits |
| system.cpu1.dcache.demand_mshr_hits::cpu1.data 391193 # number of demand (read+write) MSHR hits |
| system.cpu1.dcache.demand_mshr_hits::total 391193 # number of demand (read+write) MSHR hits |
| system.cpu1.dcache.overall_mshr_hits::cpu1.data 391193 # number of overall MSHR hits |
| system.cpu1.dcache.overall_mshr_hits::total 391193 # number of overall MSHR hits |
| system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93002 # number of ReadReq MSHR misses |
| system.cpu1.dcache.ReadReq_mshr_misses::total 93002 # number of ReadReq MSHR misses |
| system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48400 # number of WriteReq MSHR misses |
| system.cpu1.dcache.WriteReq_mshr_misses::total 48400 # number of WriteReq MSHR misses |
| system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4468 # number of LoadLockedReq MSHR misses |
| system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4468 # number of LoadLockedReq MSHR misses |
| system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3088 # number of StoreCondReq MSHR misses |
| system.cpu1.dcache.StoreCondReq_mshr_misses::total 3088 # number of StoreCondReq MSHR misses |
| system.cpu1.dcache.demand_mshr_misses::cpu1.data 141402 # number of demand (read+write) MSHR misses |
| system.cpu1.dcache.demand_mshr_misses::total 141402 # number of demand (read+write) MSHR misses |
| system.cpu1.dcache.overall_mshr_misses::cpu1.data 141402 # number of overall MSHR misses |
| system.cpu1.dcache.overall_mshr_misses::total 141402 # number of overall MSHR misses |
| system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable |
| system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable |
| system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable |
| system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3156 # number of WriteReq MSHR uncacheable |
| system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses |
| system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3374 # number of overall MSHR uncacheable misses |
| system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1257789500 # number of ReadReq MSHR miss cycles |
| system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1257789500 # number of ReadReq MSHR miss cycles |
| system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1961692747 # number of WriteReq MSHR miss cycles |
| system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1961692747 # number of WriteReq MSHR miss cycles |
| system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39632000 # number of LoadLockedReq MSHR miss cycles |
| system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39632000 # number of LoadLockedReq MSHR miss cycles |
| system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14049500 # number of StoreCondReq MSHR miss cycles |
| system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14049500 # number of StoreCondReq MSHR miss cycles |
| system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3219482247 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.dcache.demand_mshr_miss_latency::total 3219482247 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3219482247 # number of overall MSHR miss cycles |
| system.cpu1.dcache.overall_mshr_miss_latency::total 3219482247 # number of overall MSHR miss cycles |
| system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41842500 # number of ReadReq MSHR uncacheable cycles |
| system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41842500 # number of ReadReq MSHR uncacheable cycles |
| system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41842500 # number of overall MSHR uncacheable cycles |
| system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41842500 # number of overall MSHR uncacheable cycles |
| system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042617 # mshr miss rate for ReadReq accesses |
| system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042617 # mshr miss rate for ReadReq accesses |
| system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses |
| system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses |
| system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097440 # mshr miss rate for LoadLockedReq accesses |
| system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097440 # mshr miss rate for LoadLockedReq accesses |
| system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076574 # mshr miss rate for StoreCondReq accesses |
| system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076574 # mshr miss rate for StoreCondReq accesses |
| system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for demand accesses |
| system.cpu1.dcache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses |
| system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for overall accesses |
| system.cpu1.dcache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses |
| system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434 # average ReadReq mshr miss latency |
| system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434 # average ReadReq mshr miss latency |
| system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880 # average WriteReq mshr miss latency |
| system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880 # average WriteReq mshr miss latency |
| system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8870.188004 # average LoadLockedReq mshr miss latency |
| system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8870.188004 # average LoadLockedReq mshr miss latency |
| system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.708549 # average StoreCondReq mshr miss latency |
| system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.708549 # average StoreCondReq mshr miss latency |
| system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency |
| system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency |
| system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency |
| system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency |
| system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394 # average ReadReq mshr uncacheable latency |
| system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394 # average ReadReq mshr uncacheable latency |
| system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282 # average overall mshr uncacheable latency |
| system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282 # average overall mshr uncacheable latency |
| system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu1.icache.tags.replacements 256309 # number of replacements |
| system.cpu1.icache.tags.tagsinuse 470.814625 # Cycle average of tags in use |
| system.cpu1.icache.tags.total_refs 1714023 # Total number of references to valid blocks. |
| system.cpu1.icache.tags.sampled_refs 256821 # Sample count of references to valid blocks. |
| system.cpu1.icache.tags.avg_refs 6.673999 # Average number of references to valid blocks. |
| system.cpu1.icache.tags.warmup_cycle 1883968823500 # Cycle when the warmup percentage was hit. |
| system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.814625 # Average occupied blocks per requestor |
| system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919560 # Average percentage of cache occupancy |
| system.cpu1.icache.tags.occ_percent::total 0.919560 # Average percentage of cache occupancy |
| system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id |
| system.cpu1.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id |
| system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id |
| system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu1.icache.tags.tag_accesses 2239848 # Number of tag accesses |
| system.cpu1.icache.tags.data_accesses 2239848 # Number of data accesses |
| system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu1.icache.ReadReq_hits::cpu1.inst 1714023 # number of ReadReq hits |
| system.cpu1.icache.ReadReq_hits::total 1714023 # number of ReadReq hits |
| system.cpu1.icache.demand_hits::cpu1.inst 1714023 # number of demand (read+write) hits |
| system.cpu1.icache.demand_hits::total 1714023 # number of demand (read+write) hits |
| system.cpu1.icache.overall_hits::cpu1.inst 1714023 # number of overall hits |
| system.cpu1.icache.overall_hits::total 1714023 # number of overall hits |
| system.cpu1.icache.ReadReq_misses::cpu1.inst 268930 # number of ReadReq misses |
| system.cpu1.icache.ReadReq_misses::total 268930 # number of ReadReq misses |
| system.cpu1.icache.demand_misses::cpu1.inst 268930 # number of demand (read+write) misses |
| system.cpu1.icache.demand_misses::total 268930 # number of demand (read+write) misses |
| system.cpu1.icache.overall_misses::cpu1.inst 268930 # number of overall misses |
| system.cpu1.icache.overall_misses::total 268930 # number of overall misses |
| system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3748012499 # number of ReadReq miss cycles |
| system.cpu1.icache.ReadReq_miss_latency::total 3748012499 # number of ReadReq miss cycles |
| system.cpu1.icache.demand_miss_latency::cpu1.inst 3748012499 # number of demand (read+write) miss cycles |
| system.cpu1.icache.demand_miss_latency::total 3748012499 # number of demand (read+write) miss cycles |
| system.cpu1.icache.overall_miss_latency::cpu1.inst 3748012499 # number of overall miss cycles |
| system.cpu1.icache.overall_miss_latency::total 3748012499 # number of overall miss cycles |
| system.cpu1.icache.ReadReq_accesses::cpu1.inst 1982953 # number of ReadReq accesses(hits+misses) |
| system.cpu1.icache.ReadReq_accesses::total 1982953 # number of ReadReq accesses(hits+misses) |
| system.cpu1.icache.demand_accesses::cpu1.inst 1982953 # number of demand (read+write) accesses |
| system.cpu1.icache.demand_accesses::total 1982953 # number of demand (read+write) accesses |
| system.cpu1.icache.overall_accesses::cpu1.inst 1982953 # number of overall (read+write) accesses |
| system.cpu1.icache.overall_accesses::total 1982953 # number of overall (read+write) accesses |
| system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.135621 # miss rate for ReadReq accesses |
| system.cpu1.icache.ReadReq_miss_rate::total 0.135621 # miss rate for ReadReq accesses |
| system.cpu1.icache.demand_miss_rate::cpu1.inst 0.135621 # miss rate for demand accesses |
| system.cpu1.icache.demand_miss_rate::total 0.135621 # miss rate for demand accesses |
| system.cpu1.icache.overall_miss_rate::cpu1.inst 0.135621 # miss rate for overall accesses |
| system.cpu1.icache.overall_miss_rate::total 0.135621 # miss rate for overall accesses |
| system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632 # average ReadReq miss latency |
| system.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632 # average ReadReq miss latency |
| system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency |
| system.cpu1.icache.demand_avg_miss_latency::total 13936.758632 # average overall miss latency |
| system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency |
| system.cpu1.icache.overall_avg_miss_latency::total 13936.758632 # average overall miss latency |
| system.cpu1.icache.blocked_cycles::no_mshrs 558 # number of cycles access was blocked |
| system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu1.icache.blocked::no_mshrs 46 # number of cycles access was blocked |
| system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.130435 # average number of cycles each access was blocked |
| system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu1.icache.writebacks::writebacks 256309 # number of writebacks |
| system.cpu1.icache.writebacks::total 256309 # number of writebacks |
| system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12035 # number of ReadReq MSHR hits |
| system.cpu1.icache.ReadReq_mshr_hits::total 12035 # number of ReadReq MSHR hits |
| system.cpu1.icache.demand_mshr_hits::cpu1.inst 12035 # number of demand (read+write) MSHR hits |
| system.cpu1.icache.demand_mshr_hits::total 12035 # number of demand (read+write) MSHR hits |
| system.cpu1.icache.overall_mshr_hits::cpu1.inst 12035 # number of overall MSHR hits |
| system.cpu1.icache.overall_mshr_hits::total 12035 # number of overall MSHR hits |
| system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 256895 # number of ReadReq MSHR misses |
| system.cpu1.icache.ReadReq_mshr_misses::total 256895 # number of ReadReq MSHR misses |
| system.cpu1.icache.demand_mshr_misses::cpu1.inst 256895 # number of demand (read+write) MSHR misses |
| system.cpu1.icache.demand_mshr_misses::total 256895 # number of demand (read+write) MSHR misses |
| system.cpu1.icache.overall_mshr_misses::cpu1.inst 256895 # number of overall MSHR misses |
| system.cpu1.icache.overall_mshr_misses::total 256895 # number of overall MSHR misses |
| system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3358325499 # number of ReadReq MSHR miss cycles |
| system.cpu1.icache.ReadReq_mshr_miss_latency::total 3358325499 # number of ReadReq MSHR miss cycles |
| system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3358325499 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.icache.demand_mshr_miss_latency::total 3358325499 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3358325499 # number of overall MSHR miss cycles |
| system.cpu1.icache.overall_mshr_miss_latency::total 3358325499 # number of overall MSHR miss cycles |
| system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for ReadReq accesses |
| system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129552 # mshr miss rate for ReadReq accesses |
| system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for demand accesses |
| system.cpu1.icache.demand_mshr_miss_rate::total 0.129552 # mshr miss rate for demand accesses |
| system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for overall accesses |
| system.cpu1.icache.overall_mshr_miss_rate::total 0.129552 # mshr miss rate for overall accesses |
| system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average ReadReq mshr miss latency |
| system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402 # average ReadReq mshr miss latency |
| system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency |
| system.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency |
| system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency |
| system.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency |
| system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). |
| system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). |
| system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. |
| system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. |
| system.disk0.dma_write_txs 395 # Number of DMA write transactions. |
| system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). |
| system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). |
| system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. |
| system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. |
| system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| system.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.iobus.trans_dist::ReadReq 7374 # Transaction distribution |
| system.iobus.trans_dist::ReadResp 7374 # Transaction distribution |
| system.iobus.trans_dist::WriteReq 54617 # Transaction distribution |
| system.iobus.trans_dist::WriteResp 54617 # Transaction distribution |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11920 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.bridge.master::total 40520 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47680 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.bridge.master::total 73906 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) |
| system.iobus.reqLayer0.occupancy 12368500 # Layer occupancy (ticks) |
| system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) |
| system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) |
| system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) |
| system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer22.occupancy 176500 # Layer occupancy (ticks) |
| system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer23.occupancy 14153500 # Layer occupancy (ticks) |
| system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer24.occupancy 2825500 # Layer occupancy (ticks) |
| system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer25.occupancy 6058000 # Layer occupancy (ticks) |
| system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) |
| system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| system.iobus.reqLayer27.occupancy 216256520 # Layer occupancy (ticks) |
| system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| system.iobus.respLayer0.occupancy 27455000 # Layer occupancy (ticks) |
| system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) |
| system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.iocache.tags.replacements 41699 # number of replacements |
| system.iocache.tags.tagsinuse 0.514549 # Cycle average of tags in use |
| system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. |
| system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| system.iocache.tags.warmup_cycle 1714263350000 # Cycle when the warmup percentage was hit. |
| system.iocache.tags.occ_blocks::tsunami.ide 0.514549 # Average occupied blocks per requestor |
| system.iocache.tags.occ_percent::tsunami.ide 0.032159 # Average percentage of cache occupancy |
| system.iocache.tags.occ_percent::total 0.032159 # Average percentage of cache occupancy |
| system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |
| system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id |
| system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| system.iocache.tags.tag_accesses 375579 # Number of tag accesses |
| system.iocache.tags.data_accesses 375579 # Number of data accesses |
| system.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses |
| system.iocache.ReadReq_misses::total 179 # number of ReadReq misses |
| system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses |
| system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses |
| system.iocache.demand_misses::total 41731 # number of demand (read+write) misses |
| system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses |
| system.iocache.overall_misses::total 41731 # number of overall misses |
| system.iocache.ReadReq_miss_latency::tsunami.ide 22652883 # number of ReadReq miss cycles |
| system.iocache.ReadReq_miss_latency::total 22652883 # number of ReadReq miss cycles |
| system.iocache.WriteLineReq_miss_latency::tsunami.ide 4915863637 # number of WriteLineReq miss cycles |
| system.iocache.WriteLineReq_miss_latency::total 4915863637 # number of WriteLineReq miss cycles |
| system.iocache.demand_miss_latency::tsunami.ide 4938516520 # number of demand (read+write) miss cycles |
| system.iocache.demand_miss_latency::total 4938516520 # number of demand (read+write) miss cycles |
| system.iocache.overall_miss_latency::tsunami.ide 4938516520 # number of overall miss cycles |
| system.iocache.overall_miss_latency::total 4938516520 # number of overall miss cycles |
| system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) |
| system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) |
| system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) |
| system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses |
| system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses |
| system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses |
| system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses |
| system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses |
| system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses |
| system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses |
| system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses |
| system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
| system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses |
| system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994 # average ReadReq miss latency |
| system.iocache.ReadReq_avg_miss_latency::total 126552.418994 # average ReadReq miss latency |
| system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243 # average WriteLineReq miss latency |
| system.iocache.WriteLineReq_avg_miss_latency::total 118306.306243 # average WriteLineReq miss latency |
| system.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency |
| system.iocache.demand_avg_miss_latency::total 118341.676931 # average overall miss latency |
| system.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency |
| system.iocache.overall_avg_miss_latency::total 118341.676931 # average overall miss latency |
| system.iocache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked |
| system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked |
| system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| system.iocache.avg_blocked_cycles::no_mshrs 173.750000 # average number of cycles each access was blocked |
| system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.iocache.writebacks::writebacks 41520 # number of writebacks |
| system.iocache.writebacks::total 41520 # number of writebacks |
| system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses |
| system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses |
| system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses |
| system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses |
| system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses |
| system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses |
| system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses |
| system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13702883 # number of ReadReq MSHR miss cycles |
| system.iocache.ReadReq_mshr_miss_latency::total 13702883 # number of ReadReq MSHR miss cycles |
| system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2835827584 # number of WriteLineReq MSHR miss cycles |
| system.iocache.WriteLineReq_mshr_miss_latency::total 2835827584 # number of WriteLineReq MSHR miss cycles |
| system.iocache.demand_mshr_miss_latency::tsunami.ide 2849530467 # number of demand (read+write) MSHR miss cycles |
| system.iocache.demand_mshr_miss_latency::total 2849530467 # number of demand (read+write) MSHR miss cycles |
| system.iocache.overall_mshr_miss_latency::tsunami.ide 2849530467 # number of overall MSHR miss cycles |
| system.iocache.overall_mshr_miss_latency::total 2849530467 # number of overall MSHR miss cycles |
| system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses |
| system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses |
| system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses |
| system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses |
| system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses |
| system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses |
| system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994 # average ReadReq mshr miss latency |
| system.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994 # average ReadReq mshr miss latency |
| system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630 # average WriteLineReq mshr miss latency |
| system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630 # average WriteLineReq mshr miss latency |
| system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency |
| system.iocache.demand_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency |
| system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency |
| system.iocache.overall_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency |
| system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.l2c.tags.replacements 345895 # number of replacements |
| system.l2c.tags.tagsinuse 65423.250509 # Cycle average of tags in use |
| system.l2c.tags.total_refs 4330734 # Total number of references to valid blocks. |
| system.l2c.tags.sampled_refs 411417 # Sample count of references to valid blocks. |
| system.l2c.tags.avg_refs 10.526386 # Average number of references to valid blocks. |
| system.l2c.tags.warmup_cycle 6416604000 # Cycle when the warmup percentage was hit. |
| system.l2c.tags.occ_blocks::writebacks 292.398395 # Average occupied blocks per requestor |
| system.l2c.tags.occ_blocks::cpu0.inst 5320.578215 # Average occupied blocks per requestor |
| system.l2c.tags.occ_blocks::cpu0.data 58825.194930 # Average occupied blocks per requestor |
| system.l2c.tags.occ_blocks::cpu1.inst 208.100344 # Average occupied blocks per requestor |
| system.l2c.tags.occ_blocks::cpu1.data 776.978626 # Average occupied blocks per requestor |
| system.l2c.tags.occ_percent::writebacks 0.004462 # Average percentage of cache occupancy |
| system.l2c.tags.occ_percent::cpu0.inst 0.081186 # Average percentage of cache occupancy |
| system.l2c.tags.occ_percent::cpu0.data 0.897601 # Average percentage of cache occupancy |
| system.l2c.tags.occ_percent::cpu1.inst 0.003175 # Average percentage of cache occupancy |
| system.l2c.tags.occ_percent::cpu1.data 0.011856 # Average percentage of cache occupancy |
| system.l2c.tags.occ_percent::total 0.998280 # Average percentage of cache occupancy |
| system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id |
| system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id |
| system.l2c.tags.age_task_id_blocks_1024::1 1663 # Occupied blocks per task id |
| system.l2c.tags.age_task_id_blocks_1024::2 1868 # Occupied blocks per task id |
| system.l2c.tags.age_task_id_blocks_1024::3 5665 # Occupied blocks per task id |
| system.l2c.tags.age_task_id_blocks_1024::4 56191 # Occupied blocks per task id |
| system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id |
| system.l2c.tags.tag_accesses 38351741 # Number of tag accesses |
| system.l2c.tags.data_accesses 38351741 # Number of data accesses |
| system.l2c.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.l2c.WritebackDirty_hits::writebacks 822397 # number of WritebackDirty hits |
| system.l2c.WritebackDirty_hits::total 822397 # number of WritebackDirty hits |
| system.l2c.WritebackClean_hits::writebacks 872029 # number of WritebackClean hits |
| system.l2c.WritebackClean_hits::total 872029 # number of WritebackClean hits |
| system.l2c.UpgradeReq_hits::cpu0.data 2840 # number of UpgradeReq hits |
| system.l2c.UpgradeReq_hits::cpu1.data 1502 # number of UpgradeReq hits |
| system.l2c.UpgradeReq_hits::total 4342 # number of UpgradeReq hits |
| system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits |
| system.l2c.SCUpgradeReq_hits::cpu1.data 466 # number of SCUpgradeReq hits |
| system.l2c.SCUpgradeReq_hits::total 967 # number of SCUpgradeReq hits |
| system.l2c.ReadExReq_hits::cpu0.data 145832 # number of ReadExReq hits |
| system.l2c.ReadExReq_hits::cpu1.data 30945 # number of ReadExReq hits |
| system.l2c.ReadExReq_hits::total 176777 # number of ReadExReq hits |
| system.l2c.ReadCleanReq_hits::cpu0.inst 879111 # number of ReadCleanReq hits |
| system.l2c.ReadCleanReq_hits::cpu1.inst 254952 # number of ReadCleanReq hits |
| system.l2c.ReadCleanReq_hits::total 1134063 # number of ReadCleanReq hits |
| system.l2c.ReadSharedReq_hits::cpu0.data 723239 # number of ReadSharedReq hits |
| system.l2c.ReadSharedReq_hits::cpu1.data 83990 # number of ReadSharedReq hits |
| system.l2c.ReadSharedReq_hits::total 807229 # number of ReadSharedReq hits |
| system.l2c.demand_hits::cpu0.inst 879111 # number of demand (read+write) hits |
| system.l2c.demand_hits::cpu0.data 869071 # number of demand (read+write) hits |
| system.l2c.demand_hits::cpu1.inst 254952 # number of demand (read+write) hits |
| system.l2c.demand_hits::cpu1.data 114935 # number of demand (read+write) hits |
| system.l2c.demand_hits::total 2118069 # number of demand (read+write) hits |
| system.l2c.overall_hits::cpu0.inst 879111 # number of overall hits |
| system.l2c.overall_hits::cpu0.data 869071 # number of overall hits |
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| system.l2c.ReadCleanReq_misses::cpu1.inst 1902 # number of ReadCleanReq misses |
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| system.l2c.overall_miss_latency::cpu1.data 1756582500 # number of overall miss cycles |
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| system.l2c.WritebackDirty_accesses::total 822397 # number of WritebackDirty accesses(hits+misses) |
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| system.l2c.WritebackClean_accesses::total 872029 # number of WritebackClean accesses(hits+misses) |
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| system.l2c.overall_accesses::total 2529534 # number of overall (read+write) accesses |
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| system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003318 # miss rate for UpgradeReq accesses |
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| system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002141 # miss rate for SCUpgradeReq accesses |
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| system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007405 # miss rate for ReadCleanReq accesses |
| system.l2c.ReadCleanReq_miss_rate::total 0.013301 # miss rate for ReadCleanReq accesses |
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| system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022895 # miss rate for ReadSharedReq accesses |
| system.l2c.ReadSharedReq_miss_rate::total 0.253767 # miss rate for ReadSharedReq accesses |
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| system.l2c.demand_miss_rate::cpu1.data 0.108789 # miss rate for demand accesses |
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| system.l2c.overall_miss_rate::cpu1.data 0.108789 # miss rate for overall accesses |
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| system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23200 # average UpgradeReq miss latency |
| system.l2c.UpgradeReq_avg_miss_latency::total 39791.666667 # average UpgradeReq miss latency |
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| system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126972.351186 # average ReadExReq miss latency |
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| system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 98854.626709 # average ReadCleanReq miss latency |
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| system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 114350.609756 # average ReadSharedReq miss latency |
| system.l2c.ReadSharedReq_avg_miss_latency::total 81609.888929 # average ReadSharedReq miss latency |
| system.l2c.demand_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency |
| system.l2c.demand_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency |
| system.l2c.demand_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency |
| system.l2c.demand_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency |
| system.l2c.demand_avg_miss_latency::total 89423.543922 # average overall miss latency |
| system.l2c.overall_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency |
| system.l2c.overall_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency |
| system.l2c.overall_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency |
| system.l2c.overall_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency |
| system.l2c.overall_avg_miss_latency::total 89423.543922 # average overall miss latency |
| system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.l2c.writebacks::writebacks 82068 # number of writebacks |
| system.l2c.writebacks::total 82068 # number of writebacks |
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| system.l2c.ReadCleanReq_mshr_hits::total 16 # number of ReadCleanReq MSHR hits |
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| system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits |
| system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits |
| system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits |
| system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits |
| system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits |
| system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits |
| system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses |
| system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses |
| system.l2c.UpgradeReq_mshr_misses::cpu0.data 7 # number of UpgradeReq MSHR misses |
| system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses |
| system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses |
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| system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1886 # number of ReadCleanReq MSHR misses |
| system.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses |
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| system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1967 # number of ReadSharedReq MSHR misses |
| system.l2c.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses |
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| system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses |
| system.l2c.demand_mshr_misses::total 411448 # number of demand (read+write) MSHR misses |
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| system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses |
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| system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable |
| system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable |
| system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable |
| system.l2c.WriteReq_mshr_uncacheable::total 13065 # number of WriteReq MSHR uncacheable |
| system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses |
| system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses |
| system.l2c.overall_mshr_uncacheable_misses::total 20260 # number of overall MSHR uncacheable misses |
| system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 291500 # number of UpgradeReq MSHR miss cycles |
| system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94500 # number of UpgradeReq MSHR miss cycles |
| system.l2c.UpgradeReq_mshr_miss_latency::total 386000 # number of UpgradeReq MSHR miss cycles |
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| system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles |
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| system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 167908000 # number of ReadCleanReq MSHR miss cycles |
| system.l2c.ReadCleanReq_mshr_miss_latency::total 1379717000 # number of ReadCleanReq MSHR miss cycles |
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| system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 205283000 # number of ReadSharedReq MSHR miss cycles |
| system.l2c.ReadSharedReq_mshr_miss_latency::total 19663362003 # number of ReadSharedReq MSHR miss cycles |
| system.l2c.demand_mshr_miss_latency::cpu0.inst 1211809000 # number of demand (read+write) MSHR miss cycles |
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| system.l2c.demand_mshr_miss_latency::cpu1.data 1616203500 # number of demand (read+write) MSHR miss cycles |
| system.l2c.demand_mshr_miss_latency::total 32684718003 # number of demand (read+write) MSHR miss cycles |
| system.l2c.overall_mshr_miss_latency::cpu0.inst 1211809000 # number of overall MSHR miss cycles |
| system.l2c.overall_mshr_miss_latency::cpu0.data 29688797503 # number of overall MSHR miss cycles |
| system.l2c.overall_mshr_miss_latency::cpu1.inst 167908000 # number of overall MSHR miss cycles |
| system.l2c.overall_mshr_miss_latency::cpu1.data 1616203500 # number of overall MSHR miss cycles |
| system.l2c.overall_mshr_miss_latency::total 32684718003 # number of overall MSHR miss cycles |
| system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1470022500 # number of ReadReq MSHR uncacheable cycles |
| system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39117500 # number of ReadReq MSHR uncacheable cycles |
| system.l2c.ReadReq_mshr_uncacheable_latency::total 1509140000 # number of ReadReq MSHR uncacheable cycles |
| system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1470022500 # number of overall MSHR uncacheable cycles |
| system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39117500 # number of overall MSHR uncacheable cycles |
| system.l2c.overall_mshr_uncacheable_latency::total 1509140000 # number of overall MSHR uncacheable cycles |
| system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses |
| system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002459 # mshr miss rate for UpgradeReq accesses |
| system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003318 # mshr miss rate for UpgradeReq accesses |
| system.l2c.UpgradeReq_mshr_miss_rate::total 0.002756 # mshr miss rate for UpgradeReq accesses |
| system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002141 # mshr miss rate for SCUpgradeReq accesses |
| system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001033 # mshr miss rate for SCUpgradeReq accesses |
| system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.429093 # mshr miss rate for ReadExReq accesses |
| system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280466 # mshr miss rate for ReadExReq accesses |
| system.l2c.ReadExReq_mshr_miss_rate::total 0.407675 # mshr miss rate for ReadExReq accesses |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for ReadCleanReq accesses |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for ReadCleanReq accesses |
| system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013287 # mshr miss rate for ReadCleanReq accesses |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273696 # mshr miss rate for ReadSharedReq accesses |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022883 # mshr miss rate for ReadSharedReq accesses |
| system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253766 # mshr miss rate for ReadSharedReq accesses |
| system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for demand accesses |
| system.l2c.demand_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for demand accesses |
| system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for demand accesses |
| system.l2c.demand_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for demand accesses |
| system.l2c.demand_mshr_miss_rate::total 0.162658 # mshr miss rate for demand accesses |
| system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for overall accesses |
| system.l2c.overall_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for overall accesses |
| system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for overall accesses |
| system.l2c.overall_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for overall accesses |
| system.l2c.overall_mshr_miss_rate::total 0.162658 # mshr miss rate for overall accesses |
| system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143 # average UpgradeReq mshr miss latency |
| system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18900 # average UpgradeReq mshr miss latency |
| system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667 # average UpgradeReq mshr miss latency |
| system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency |
| system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218 # average ReadExReq mshr miss latency |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186 # average ReadExReq mshr miss latency |
| system.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096 # average ReadExReq mshr miss latency |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average ReadCleanReq mshr miss latency |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average ReadCleanReq mshr miss latency |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118 # average ReadCleanReq mshr miss latency |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499 # average ReadSharedReq mshr miss latency |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712 # average ReadSharedReq mshr miss latency |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445 # average ReadSharedReq mshr miss latency |
| system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency |
| system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency |
| system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency |
| system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency |
| system.l2c.demand_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency |
| system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498 # average ReadReq mshr uncacheable latency |
| system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394 # average ReadReq mshr uncacheable latency |
| system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414 # average ReadReq mshr uncacheable latency |
| system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027 # average overall mshr uncacheable latency |
| system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572 # average overall mshr uncacheable latency |
| system.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581 # average overall mshr uncacheable latency |
| system.membus.snoop_filter.tot_requests 851998 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 399673 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadReq 7195 # Transaction distribution |
| system.membus.trans_dist::ReadResp 297108 # Transaction distribution |
| system.membus.trans_dist::WriteReq 13065 # Transaction distribution |
| system.membus.trans_dist::WriteResp 13065 # Transaction distribution |
| system.membus.trans_dist::WritebackDirty 123588 # Transaction distribution |
| system.membus.trans_dist::CleanEvict 263109 # Transaction distribution |
| system.membus.trans_dist::UpgradeReq 6612 # Transaction distribution |
| system.membus.trans_dist::SCUpgradeReq 5150 # Transaction distribution |
| system.membus.trans_dist::UpgradeResp 3 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 121960 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 121558 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 289958 # Transaction distribution |
| system.membus.trans_dist::BadAddressError 45 # Transaction distribution |
| system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| system.membus.trans_dist::InvalidateResp 134 # Transaction distribution |
| system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40520 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179462 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count_system.l2c.mem_side::total 1220072 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 1303517 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73906 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31556864 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size_system.l2c.mem_side::total 31630770 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 34289010 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 12625 # Total snoops (count) |
| system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 485492 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0.001421 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0.037673 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 484802 99.86% 99.86% # Request fanout histogram |
| system.membus.snoop_fanout::1 690 0.14% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| system.membus.snoop_fanout::total 485492 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 36514000 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.membus.reqLayer1.occupancy 1353680299 # Layer occupancy (ticks) |
| system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| system.membus.reqLayer2.occupancy 56000 # Layer occupancy (ticks) |
| system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 2179395750 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| system.membus.respLayer2.occupancy 1105081 # Layer occupancy (ticks) |
| system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.toL2Bus.snoop_filter.tot_requests 5103450 # Total number of requests made to the snoop filter. |
| system.toL2Bus.snoop_filter.hit_single_requests 2546310 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.toL2Bus.snoop_filter.hit_multi_requests 356575 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. |
| system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution |
| system.toL2Bus.trans_dist::ReadResp 2260935 # Transaction distribution |
| system.toL2Bus.trans_dist::WriteReq 13065 # Transaction distribution |
| system.toL2Bus.trans_dist::WriteResp 13065 # Transaction distribution |
| system.toL2Bus.trans_dist::WritebackDirty 904465 # Transaction distribution |
| system.toL2Bus.trans_dist::WritebackClean 1148228 # Transaction distribution |
| system.toL2Bus.trans_dist::CleanEvict 826225 # Transaction distribution |
| system.toL2Bus.trans_dist::UpgradeReq 10843 # Transaction distribution |
| system.toL2Bus.trans_dist::SCUpgradeReq 6117 # Transaction distribution |
| system.toL2Bus.trans_dist::UpgradeResp 16960 # Transaction distribution |
| system.toL2Bus.trans_dist::ReadExReq 299845 # Transaction distribution |
| system.toL2Bus.trans_dist::ReadExResp 299845 # Transaction distribution |
| system.toL2Bus.trans_dist::ReadCleanReq 1149557 # Transaction distribution |
| system.toL2Bus.trans_dist::ReadSharedReq 1104232 # Transaction distribution |
| system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution |
| system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution |
| system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution |
| system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2677077 # Packet count per connected master and slave (bytes) |
| system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3814281 # Packet count per connected master and slave (bytes) |
| system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 770058 # Packet count per connected master and slave (bytes) |
| system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417575 # Packet count per connected master and slave (bytes) |
| system.toL2Bus.pkt_count::total 7678991 # Packet count per connected master and slave (bytes) |
| system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114202560 # Cumulative packet size per connected master and slave (bytes) |
| system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127366412 # Cumulative packet size per connected master and slave (bytes) |
| system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32842432 # Cumulative packet size per connected master and slave (bytes) |
| system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13680230 # Cumulative packet size per connected master and slave (bytes) |
| system.toL2Bus.pkt_size::total 288091634 # Cumulative packet size per connected master and slave (bytes) |
| system.toL2Bus.snoops 382034 # Total snoops (count) |
| system.toL2Bus.snoopTraffic 6794496 # Total snoop traffic (bytes) |
| system.toL2Bus.snoop_fanout::samples 2936985 # Request fanout histogram |
| system.toL2Bus.snoop_fanout::mean 0.126280 # Request fanout histogram |
| system.toL2Bus.snoop_fanout::stdev 0.332605 # Request fanout histogram |
| system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::0 2566512 87.39% 87.39% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::1 370085 12.60% 99.99% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::2 367 0.01% 100.00% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::3 21 0.00% 100.00% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| system.toL2Bus.snoop_fanout::total 2936985 # Request fanout histogram |
| system.toL2Bus.reqLayer0.occupancy 4539093837 # Layer occupancy (ticks) |
| system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| system.toL2Bus.snoopLayer0.occupancy 303384 # Layer occupancy (ticks) |
| system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| system.toL2Bus.respLayer0.occupancy 1340375720 # Layer occupancy (ticks) |
| system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| system.toL2Bus.respLayer1.occupancy 1912124205 # Layer occupancy (ticks) |
| system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| system.toL2Bus.respLayer2.occupancy 386934286 # Layer occupancy (ticks) |
| system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| system.toL2Bus.respLayer3.occupancy 217615473 # Layer occupancy (ticks) |
| system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA |
| system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |
| system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |
| system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA |
| system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR |
| system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR |
| system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR |
| system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR |
| system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR |
| system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR |
| system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR |
| system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU |
| system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states |
| system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| system.cpu0.kern.inst.quiesce 6479 # number of quiesce instructions executed |
| system.cpu0.kern.inst.hwrei 176756 # number of hwrei instructions executed |
| system.cpu0.kern.ipl_count::0 62790 40.27% 40.27% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count::22 1928 1.24% 41.59% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count::31 90883 58.29% 100.00% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count::total 155913 # number of times we switched to this ipl |
| system.cpu0.kern.ipl_good::0 61775 49.18% 49.18% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good::21 131 0.10% 49.28% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good::22 1928 1.53% 50.82% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good::31 61594 49.04% 100.00% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good::total 125609 # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_ticks::0 1865241808000 97.65% 97.65% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks::21 64326000 0.00% 97.65% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks::22 577244500 0.03% 97.68% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks::30 87620000 0.00% 97.69% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks::31 44188694000 2.31% 100.00% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks::total 1910159692500 # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_used::0 0.983835 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used::31 0.677729 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used::total 0.805635 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed |
| system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed |
| system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed |
| system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed |
| system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed |
| system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed |
| system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed |
| system.cpu0.kern.callpal::swpipl 149358 91.35% 93.61% # number of callpals executed |
| system.cpu0.kern.callpal::rdps 5686 3.48% 97.09% # number of callpals executed |
| system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed |
| system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed |
| system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed |
| system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed |
| system.cpu0.kern.callpal::rti 4314 2.64% 99.73% # number of callpals executed |
| system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed |
| system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed |
| system.cpu0.kern.callpal::total 163506 # number of callpals executed |
| system.cpu0.kern.mode_switch::kernel 6667 # number of protection mode switches |
| system.cpu0.kern.mode_switch::user 1071 # number of protection mode switches |
| system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| system.cpu0.kern.mode_good::kernel 1071 |
| system.cpu0.kern.mode_good::user 1071 |
| system.cpu0.kern.mode_good::idle 0 |
| system.cpu0.kern.mode_switch_good::kernel 0.160642 # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good::total 0.276816 # fraction of useful protection mode switches |
| system.cpu0.kern.mode_ticks::kernel 1908119380500 99.91% 99.91% # number of ticks spent at the given mode |
| system.cpu0.kern.mode_ticks::user 1686628500 0.09% 100.00% # number of ticks spent at the given mode |
| system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| system.cpu0.kern.swap_context 3350 # number of times the context was actually changed |
| system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| system.cpu1.kern.inst.quiesce 2544 # number of quiesce instructions executed |
| system.cpu1.kern.inst.hwrei 62917 # number of hwrei instructions executed |
| system.cpu1.kern.ipl_count::0 19565 37.60% 37.60% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count::22 1926 3.70% 41.30% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count::31 30256 58.14% 100.00% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count::total 52040 # number of times we switched to this ipl |
| system.cpu1.kern.ipl_good::0 19203 47.61% 47.61% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good::22 1926 4.78% 52.39% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good::31 18910 46.89% 100.00% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good::total 40332 # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_ticks::0 1875855078000 98.19% 98.19% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks::22 566007000 0.03% 98.22% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks::30 141529500 0.01% 98.23% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks::31 33893640500 1.77% 100.00% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks::total 1910456255000 # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_used::0 0.981498 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used::31 0.625000 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used::total 0.775019 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed |
| system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed |
| system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed |
| system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed |
| system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed |
| system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed |
| system.cpu1.kern.callpal::swpipl 46571 85.30% 87.91% # number of callpals executed |
| system.cpu1.kern.callpal::rdps 3080 5.64% 93.55% # number of callpals executed |
| system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed |
| system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed |
| system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed |
| system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed |
| system.cpu1.kern.callpal::rti 3249 5.95% 99.52% # number of callpals executed |
| system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed |
| system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed |
| system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| system.cpu1.kern.callpal::total 54596 # number of callpals executed |
| system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches |
| system.cpu1.kern.mode_switch::user 669 # number of protection mode switches |
| system.cpu1.kern.mode_switch::idle 2431 # number of protection mode switches |
| system.cpu1.kern.mode_good::kernel 888 |
| system.cpu1.kern.mode_good::user 669 |
| system.cpu1.kern.mode_good::idle 219 |
| system.cpu1.kern.mode_switch_good::kernel 0.522353 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good::idle 0.090086 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good::total 0.370000 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_ticks::kernel 5325548500 0.28% 0.28% # number of ticks spent at the given mode |
| system.cpu1.kern.mode_ticks::user 1057057500 0.06% 0.33% # number of ticks spent at the given mode |
| system.cpu1.kern.mode_ticks::idle 1904073641000 99.67% 100.00% # number of ticks spent at the given mode |
| system.cpu1.kern.swap_context 1229 # number of times the context was actually changed |
| |
| ---------- End Simulation Statistics ---------- |
