| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000024 # Number of seconds simulated |
| sim_ticks 23776000 # Number of ticks simulated |
| final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 135386 # Simulator instruction rate (inst/s) |
| host_op_rate 135348 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 503875461 # Simulator tick rate (ticks/s) |
| host_mem_usage 253920 # Number of bytes of host memory used |
| host_seconds 0.05 # Real time elapsed on the host |
| sim_insts 6385 # Number of instructions simulated |
| sim_ops 6385 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu.inst 19904 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 30976 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 19904 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 19904 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 311 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 484 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 837146703 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 1302826380 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 837146703 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 837146703 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 837146703 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 1302826380 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 484 # Number of read requests accepted |
| system.physmem.writeReqs 0 # Number of write requests accepted |
| system.physmem.readBursts 484 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 30976 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 30976 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 69 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 32 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 32 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 47 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 42 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 20 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 1 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 3 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 0 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 1 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 22 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 25 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 14 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 118 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 45 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 13 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| system.physmem.totGap 23381000 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 484 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 347.325843 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 230.027877 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 312.328054 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation |
| system.physmem.totQLat 8020750 # Total ticks spent queuing |
| system.physmem.totMemAccLat 17095750 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 2420000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 16571.80 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 35321.80 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 1302.83 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 1302.83 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 10.18 # Data bus utilization in percentage |
| system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| system.physmem.readRowHits 394 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 81.40 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| system.physmem.avgGap 48307.85 # Average gap between requests |
| system.physmem.pageHitRate 81.40 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 1756440 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 3000480 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 47040 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 7630020 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 131040 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 14776935 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 621.499816 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 16971750 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 780000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 340500 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 5886000 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 16729000 # Time in different power states |
| system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 2975400 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 7630590 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 68640 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 14960310 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 629.212344 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 16765250 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 780000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 5879250 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 16724250 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.branchPred.lookups 2851 # Number of BP lookups |
| system.cpu.branchPred.condPredicted 1679 # Number of conditional branches predicted |
| system.cpu.branchPred.condIncorrect 484 # Number of conditional branches incorrect |
| system.cpu.branchPred.BTBLookups 2196 # Number of BTB lookups |
| system.cpu.branchPred.BTBHits 719 # Number of BTB hits |
| system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.branchPred.BTBHitPct 32.741348 # BTB Hit Percentage |
| system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. |
| system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. |
| system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. |
| system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. |
| system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. |
| system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dtb.fetch_hits 0 # ITB hits |
| system.cpu.dtb.fetch_misses 0 # ITB misses |
| system.cpu.dtb.fetch_acv 0 # ITB acv |
| system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| system.cpu.dtb.read_hits 2241 # DTB read hits |
| system.cpu.dtb.read_misses 48 # DTB read misses |
| system.cpu.dtb.read_acv 0 # DTB read access violations |
| system.cpu.dtb.read_accesses 2289 # DTB read accesses |
| system.cpu.dtb.write_hits 1046 # DTB write hits |
| system.cpu.dtb.write_misses 28 # DTB write misses |
| system.cpu.dtb.write_acv 0 # DTB write access violations |
| system.cpu.dtb.write_accesses 1074 # DTB write accesses |
| system.cpu.dtb.data_hits 3287 # DTB hits |
| system.cpu.dtb.data_misses 76 # DTB misses |
| system.cpu.dtb.data_acv 0 # DTB access violations |
| system.cpu.dtb.data_accesses 3363 # DTB accesses |
| system.cpu.itb.fetch_hits 2298 # ITB hits |
| system.cpu.itb.fetch_misses 27 # ITB misses |
| system.cpu.itb.fetch_acv 0 # ITB acv |
| system.cpu.itb.fetch_accesses 2325 # ITB accesses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.read_acv 0 # DTB read access violations |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.write_acv 0 # DTB write access violations |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.data_hits 0 # DTB hits |
| system.cpu.itb.data_misses 0 # DTB misses |
| system.cpu.itb.data_acv 0 # DTB access violations |
| system.cpu.itb.data_accesses 0 # DTB accesses |
| system.cpu.workload.numSyscalls 17 # Number of system calls |
| system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.numCycles 47553 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.fetch.icacheStallCycles 8497 # Number of cycles fetch is stalled on an Icache miss |
| system.cpu.fetch.Insts 16552 # Number of instructions fetch has processed |
| system.cpu.fetch.Branches 2851 # Number of branches that fetch encountered |
| system.cpu.fetch.predictedBranches 1186 # Number of branches that fetch has predicted taken |
| system.cpu.fetch.Cycles 5772 # Number of cycles fetch has run and was not squashing or blocked |
| system.cpu.fetch.SquashCycles 1050 # Number of cycles fetch has spent squashing |
| system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps |
| system.cpu.fetch.CacheLines 2298 # Number of cache lines fetched |
| system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed |
| system.cpu.fetch.rateDist::samples 15472 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::mean 1.069804 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::stdev 2.455665 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::0 12480 80.66% 80.66% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::1 299 1.93% 82.59% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::2 231 1.49% 84.09% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::3 265 1.71% 85.80% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::4 295 1.91% 87.71% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::5 231 1.49% 89.20% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::6 280 1.81% 91.01% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::7 147 0.95% 91.96% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::8 1244 8.04% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::total 15472 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.branchRate 0.059954 # Number of branch fetches per cycle |
| system.cpu.fetch.rate 0.348075 # Number of inst fetches per cycle |
| system.cpu.decode.IdleCycles 8344 # Number of cycles decode is idle |
| system.cpu.decode.BlockedCycles 4012 # Number of cycles decode is blocked |
| system.cpu.decode.RunCycles 2454 # Number of cycles decode is running |
| system.cpu.decode.UnblockCycles 211 # Number of cycles decode is unblocking |
| system.cpu.decode.SquashCycles 451 # Number of cycles decode is squashing |
| system.cpu.decode.BranchResolved 754 # Number of times decode resolved a branch |
| system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction |
| system.cpu.decode.DecodedInsts 14992 # Number of instructions handled by decode |
| system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode |
| system.cpu.rename.SquashCycles 451 # Number of cycles rename is squashing |
| system.cpu.rename.IdleCycles 8504 # Number of cycles rename is idle |
| system.cpu.rename.BlockCycles 1836 # Number of cycles rename is blocking |
| system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst |
| system.cpu.rename.RunCycles 2480 # Number of cycles rename is running |
| system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking |
| system.cpu.rename.RenamedInsts 14425 # Number of instructions processed by rename |
| system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full |
| system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full |
| system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full |
| system.cpu.rename.SQFullEvents 1479 # Number of times rename has blocked due to SQ full |
| system.cpu.rename.RenamedOperands 10912 # Number of destination operands rename has renamed |
| system.cpu.rename.RenameLookups 17882 # Number of register rename lookups that rename has made |
| system.cpu.rename.int_rename_lookups 17873 # Number of integer rename lookups |
| system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups |
| system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed |
| system.cpu.rename.UndoneMaps 6335 # Number of HB maps that are undone due to squashing |
| system.cpu.rename.serializingInsts 28 # count of serializing insts renamed |
| system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed |
| system.cpu.rename.skidInsts 586 # count of insts added to the skid buffer |
| system.cpu.memDep0.insertedLoads 2823 # Number of loads inserted to the mem dependence unit. |
| system.cpu.memDep0.insertedStores 1299 # Number of stores inserted to the mem dependence unit. |
| system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. |
| system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. |
| system.cpu.iq.iqInstsAdded 13035 # Number of instructions added to the IQ (excludes non-spec) |
| system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ |
| system.cpu.iq.iqInstsIssued 10770 # Number of instructions issued |
| system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued |
| system.cpu.iq.iqSquashedInstsExamined 6676 # Number of squashed instructions iterated over during squash; mainly for profiling |
| system.cpu.iq.iqSquashedOperandsExamined 3655 # Number of squashed operands that are examined and possibly removed from graph |
| system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed |
| system.cpu.iq.issued_per_cycle::samples 15472 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::mean 0.696096 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::stdev 1.440906 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::0 11426 73.85% 73.85% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::1 1307 8.45% 82.30% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::2 919 5.94% 88.24% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::3 676 4.37% 92.61% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::4 515 3.33% 95.93% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::5 346 2.24% 98.17% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::6 202 1.31% 99.48% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::7 53 0.34% 99.82% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::8 28 0.18% 100.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::total 15472 # Number of insts issued each cycle |
| system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntAlu 21 14.79% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntMult 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntDiv 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMult 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMult 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdShift 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.79% # attempts to use FU when none available |
| system.cpu.iq.fu_full::MemRead 83 58.45% 73.24% # attempts to use FU when none available |
| system.cpu.iq.fu_full::MemWrite 37 26.06% 99.30% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.30% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMemWrite 1 0.70% 100.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntAlu 7179 66.66% 66.68% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.69% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued |
| system.cpu.iq.FU_type_0::MemRead 2465 22.89% 89.59% # Type of FU issued |
| system.cpu.iq.FU_type_0::MemWrite 1113 10.33% 99.93% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::total 10770 # Type of FU issued |
| system.cpu.iq.rate 0.226484 # Inst issue rate |
| system.cpu.iq.fu_busy_cnt 142 # FU busy when requested |
| system.cpu.iq.fu_busy_rate 0.013185 # FU busy rate (busy events/executed inst) |
| system.cpu.iq.int_inst_queue_reads 37150 # Number of integer instruction queue reads |
| system.cpu.iq.int_inst_queue_writes 19749 # Number of integer instruction queue writes |
| system.cpu.iq.int_inst_queue_wakeup_accesses 9744 # Number of integer instruction queue wakeup accesses |
| system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads |
| system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes |
| system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| system.cpu.iq.int_alu_accesses 10899 # Number of integer alu accesses |
| system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses |
| system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores |
| system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| system.cpu.iew.lsq.thread0.squashedLoads 1638 # Number of loads squashed |
| system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed |
| system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations |
| system.cpu.iew.lsq.thread0.squashedStores 434 # Number of stores squashed |
| system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked |
| system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| system.cpu.iew.iewSquashCycles 451 # Number of cycles IEW is squashing |
| system.cpu.iew.iewBlockCycles 1424 # Number of cycles IEW is blocking |
| system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking |
| system.cpu.iew.iewDispatchedInsts 13146 # Number of instructions dispatched to IQ |
| system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch |
| system.cpu.iew.iewDispLoadInsts 2823 # Number of dispatched load instructions |
| system.cpu.iew.iewDispStoreInsts 1299 # Number of dispatched store instructions |
| system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions |
| system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall |
| system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall |
| system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations |
| system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly |
| system.cpu.iew.predictedNotTakenIncorrect 389 # Number of branches that were predicted not taken incorrectly |
| system.cpu.iew.branchMispredicts 499 # Number of branch mispredicts detected at execute |
| system.cpu.iew.iewExecutedInsts 10283 # Number of executed instructions |
| system.cpu.iew.iewExecLoadInsts 2289 # Number of load instructions executed |
| system.cpu.iew.iewExecSquashedInsts 487 # Number of squashed instructions skipped in execute |
| system.cpu.iew.exec_swp 0 # number of swp insts executed |
| system.cpu.iew.exec_nop 84 # number of nop insts executed |
| system.cpu.iew.exec_refs 3373 # number of memory reference insts executed |
| system.cpu.iew.exec_branches 1639 # Number of branches executed |
| system.cpu.iew.exec_stores 1084 # Number of stores executed |
| system.cpu.iew.exec_rate 0.216243 # Inst execution rate |
| system.cpu.iew.wb_sent 9942 # cumulative count of insts sent to commit |
| system.cpu.iew.wb_count 9754 # cumulative count of insts written-back |
| system.cpu.iew.wb_producers 5150 # num instructions producing a value |
| system.cpu.iew.wb_consumers 7025 # num instructions consuming a value |
| system.cpu.iew.wb_rate 0.205118 # insts written-back per cycle |
| system.cpu.iew.wb_fanout 0.733096 # average fanout of values written-back |
| system.cpu.commit.commitSquashedInsts 6693 # The number of squashed insts skipped by commit |
| system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards |
| system.cpu.commit.branchMispredicts 410 # The number of times a branch was mispredicted |
| system.cpu.commit.committed_per_cycle::samples 14238 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::mean 0.449642 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::stdev 1.359190 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::0 11808 82.93% 82.93% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::1 1161 8.15% 91.09% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::2 469 3.29% 94.38% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::3 204 1.43% 95.81% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::4 134 0.94% 96.76% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::5 86 0.60% 97.36% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::6 97 0.68% 98.04% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::7 89 0.63% 98.67% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::8 190 1.33% 100.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::total 14238 # Number of insts commited each cycle |
| system.cpu.commit.committedInsts 6402 # Number of instructions committed |
| system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed |
| system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| system.cpu.commit.refs 2050 # Number of memory references committed |
| system.cpu.commit.loads 1185 # Number of loads committed |
| system.cpu.commit.membars 0 # Number of memory barriers committed |
| system.cpu.commit.branches 1056 # Number of branches committed |
| system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. |
| system.cpu.commit.int_insts 6319 # Number of committed integer instructions. |
| system.cpu.commit.function_calls 127 # Number of function calls committed. |
| system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction |
| system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction |
| system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction |
| system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction |
| system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction |
| system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction |
| system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction |
| system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.commit.op_class_0::total 6402 # Class of committed instruction |
| system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached |
| system.cpu.rob.rob_reads 26792 # The number of ROB reads |
| system.cpu.rob.rob_writes 27441 # The number of ROB writes |
| system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| system.cpu.idleCycles 32081 # Total number of cycles that the CPU has spent unscheduled due to idling |
| system.cpu.committedInsts 6385 # Number of Instructions Simulated |
| system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated |
| system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction |
| system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads |
| system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle |
| system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads |
| system.cpu.int_regfile_reads 13028 # number of integer regfile reads |
| system.cpu.int_regfile_writes 7426 # number of integer regfile writes |
| system.cpu.fp_regfile_reads 8 # number of floating regfile reads |
| system.cpu.fp_regfile_writes 2 # number of floating regfile writes |
| system.cpu.misc_regfile_reads 1 # number of misc regfile reads |
| system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.tags.replacements 0 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 110.199847 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 2391 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 13.820809 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 110.199847 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.026904 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.026904 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 6029 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 6029 # Number of data accesses |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.ReadReq_hits::cpu.data 1883 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 1883 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits |
| system.cpu.dcache.demand_hits::cpu.data 2391 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 2391 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 2391 # number of overall hits |
| system.cpu.dcache.overall_hits::total 2391 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses |
| system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses |
| system.cpu.dcache.overall_misses::total 537 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 13954000 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 13954000 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 31258982 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 31258982 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 45212982 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 45212982 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 45212982 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 45212982 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 2063 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087252 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.087252 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.183402 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.183402 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.183402 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.183402 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 84195.497207 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 84195.497207 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 3108 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9402500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 9402500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7030000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 7030000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16432500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 16432500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16432500 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 16432500 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048958 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048958 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.059085 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.059085 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889 # average WriteReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.tags.replacements 0 # number of replacements |
| system.cpu.icache.tags.tagsinuse 160.011089 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 1840 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 5.897436 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 160.011089 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.078130 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.078130 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.152344 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 4908 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 4908 # Number of data accesses |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.ReadReq_hits::cpu.inst 1840 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 1840 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 1840 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 1840 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 1840 # number of overall hits |
| system.cpu.icache.overall_hits::total 1840 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses |
| system.cpu.icache.overall_misses::total 458 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 35481000 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 35481000 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 35481000 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 35481000 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 35481000 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 35481000 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 2298 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 2298 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 2298 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 2298 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 2298 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 2298 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199304 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.199304 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.199304 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.199304 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.199304 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.199304 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77469.432314 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 77469.432314 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 77469.432314 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 77469.432314 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits |
| system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits |
| system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits |
| system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits |
| system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits |
| system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26195000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 26195000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26195000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 26195000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26195000 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 26195000 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135770 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.135770 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.135770 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83958.333333 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83958.333333 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.tags.replacements 0 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 270.308724 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 484 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 0.002066 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.032476 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 110.276248 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004884 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.008249 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014771 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 4364 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 4364 # Number of data accesses |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 1 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 311 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 311 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 484 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6919000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 6919000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25713500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 25713500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9242500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 9242500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 25713500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 16161500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 41875000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 25713500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 16161500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 41875000 # number of overall miss cycles |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 312 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 312 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996795 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.997938 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.997938 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 86518.595041 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 86518.595041 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 311 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 311 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6199000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6199000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22603500 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22603500 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8232500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8232500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22603500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14431500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 37035000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22603500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14431500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 37035000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996795 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.997938 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.997938 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.cpu.toL2Bus.trans_dist::ReadResp 413 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 312 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19968 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.cpu.toL2Bus.snoop_fanout::samples 485 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0.002062 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 484 99.79% 99.79% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 485 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 468000 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
| system.membus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadResp 412 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 72 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 72 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 968 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 968 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30976 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 484 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 484 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 484 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 593000 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 2566000 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 10.8 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
