| commit | f43e722238e6f0b502302b56723f55b9533ed671 | [log] [tgz] |
|---|---|---|
| author | Luming Wang <wlm199558@126.com> | Thu Sep 08 02:23:49 2022 +0000 |
| committer | Luming Wang <wlm199558@126.com> | Sat Sep 10 08:02:06 2022 +0000 |
| tree | 31398ff1489fe478fed9193d7e3e854d45124a76 | |
| parent | 6807f70b81ce77ef77017d503eb78080d03fcf62 [diff] |
cpu: Fix RAS behaviour when both isReturn and isCall are set. As discussed in [1], current BP cannot handle the instruction with both isReturn and isCall on RAS. This hurts the performance of coroutine-based programs. This patch adjusts the behaviour of RAS. When the isReturn flag is set, it will pop a RAS. Then, if the isCall flag is set, it will push a RAS. Previous implementation only pop a RAS when both isReturn and isCall are set. This behaviour follows the RISC-V Spec [2]. Since other ISAs do not have instructions that set both isCall and isReturn, this patch has no impact on other ISAs. [1] https://gem5-review.googlesource.com/c/public/gem5/+/58209 [2] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf Change-Id: I52c01bbea41347711edff9ce9a03076e46aadc92 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63311 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>