| commit | f72d22cc3830099ef5c99f0312e84b54d7296315 | [log] [tgz] |
|---|---|---|
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | Tue Feb 07 14:47:40 2023 +0000 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Wed May 17 08:11:06 2023 +0000 |
| tree | b7abc49eafcbe1514902c26f0b0af02f15c8e898 | |
| parent | bc5b00cd2b5dea850acf63f6a1055ff260c8fba7 [diff] |
arch-arm: Implement RES0/RES1 with miscreg specifiers Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>