commit f73caae20fed7b4500a724ac85c20b637ee353a1
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Nov 27 15:45:57 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Dec 11 15:07:52 2019 +0000
tree b4f10cb3e3b35bd5c71b86bc5e26120f697d5d09
parent 390a74f59934b85d91489f8a563450d8321b602d

cpu: Add byteEnable assertions to readMem and initateMemRead

Those are already present in writeMem; looking for consistency

Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>