mem: Support for separate tRCD and tCL for reads/writes

HBM2 has asynchronous read/write timings (tRCD, tCL). This change
updates dram interface in gem5 to allow using separate values of
tRCD and tCL for reads and writes.

Change-Id: I56bfa9519cedad89cc2d4c163efc7126f609f15a
Reviewed-by: Wendy Elsasser <>
Maintainer: Jason Lowe-Power <>
Reviewed-by: Jason Lowe-Power <>
Tested-by: kokoro <>
3 files changed