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import m5

from m5.objects import *

traffic_gen = PyTrafficGen()
system = System()
vd = VoltageDomain(voltage="1V")

system.mem_mode = "timing"

system.cpu = traffic_gen

dramsys = DRAMSys(
    configuration="ext/dramsys/DRAMSys/DRAMSys/"
    "library/resources/simulations/ddr4-example.json",
    resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
)

system.target = dramsys
system.transactor = Gem5ToTlmBridge32()
system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)

# Connect everything:
system.transactor.gem5 = system.cpu.port
system.transactor.tlm = system.target.tlm

kernel = SystemC_Kernel(system=system)
root = Root(full_system=False, systemc_kernel=kernel)

m5.instantiate()
idle = traffic_gen.createIdle(100000)
linear = traffic_gen.createLinear(10000000, 0, 16777216, 64, 500, 1500, 65, 0)
random = traffic_gen.createRandom(10000000, 0, 16777216, 64, 500, 1500, 65, 0)
traffic_gen.start([linear, idle, random])

cause = m5.simulate(20000000).getCause()
print(cause)