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 * All rights reserved.
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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#include "cpu/simple_thread.hh"

#include <string>

#include "arch/generic/decoder.hh"
#include "base/callback.hh"
#include "base/compiler.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/simple/base.hh"
#include "cpu/thread_context.hh"
#include "mem/se_translating_port_proxy.hh"
#include "mem/translating_port_proxy.hh"
#include "params/BaseCPU.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"

namespace gem5
{

// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                           Process *_process, BaseMMU *_mmu,
                           BaseISA *_isa, InstDecoder *_decoder)
    : ThreadState(_cpu, _thread_num, _process),
      regFiles{{
          {*_isa->regClasses().at(IntRegClass)},
          {*_isa->regClasses().at(FloatRegClass)},
          {*_isa->regClasses().at(VecRegClass)},
          {*_isa->regClasses().at(VecElemClass)},
          {*_isa->regClasses().at(VecPredRegClass)},
          {*_isa->regClasses().at(CCRegClass)}
      }},
      isa(_isa),
      predicate(true), memAccPredicate(true),
      comInstEventQueue("instruction-based event queue"),
      system(_sys), mmu(_mmu), decoder(_decoder),
      htmTransactionStarts(0), htmTransactionStops(0)
{
    clearArchRegs();
}

SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                           BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
    : SimpleThread(_cpu, _thread_num, _sys, nullptr, _mmu, _isa, _decoder)
{}

void
SimpleThread::takeOverFrom(ThreadContext *oldContext)
{
    gem5::takeOverFrom(*this, *oldContext);
    decoder->takeOverFrom(oldContext->getDecoderPtr());

    isa->takeOverFrom(this, oldContext);

    storeCondFailures = 0;
}

void
SimpleThread::copyState(ThreadContext *oldContext)
{
    // copy over functional state
    _status = oldContext->status();
    copyArchRegs(oldContext);

    _threadId = oldContext->threadId();
    _contextId = oldContext->contextId();
}

void
SimpleThread::serialize(CheckpointOut &cp) const
{
    ThreadState::serialize(cp);
    gem5::serialize(*this, cp);
}


void
SimpleThread::unserialize(CheckpointIn &cp)
{
    ThreadState::unserialize(cp);
    gem5::unserialize(*this, cp);
}

void
SimpleThread::activate()
{
    if (status() == ThreadContext::Active)
        return;

    lastActivate = curTick();
    _status = ThreadContext::Active;
    baseCpu->activateContext(_threadId);
}

void
SimpleThread::suspend()
{
    if (status() == ThreadContext::Suspended)
        return;

    lastActivate = curTick();
    lastSuspend = curTick();
    _status = ThreadContext::Suspended;
    baseCpu->suspendContext(_threadId);
}


void
SimpleThread::halt()
{
    if (status() == ThreadContext::Halted)
        return;

    _status = ThreadContext::Halted;
    baseCpu->haltContext(_threadId);
}

void
SimpleThread::copyArchRegs(ThreadContext *src_tc)
{
    getIsaPtr()->copyRegsFrom(src_tc);
}

// hardware transactional memory
void
SimpleThread::htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)
{
    baseCpu->htmSendAbortSignal(threadId(), htm_uid, cause);

    // these must be reset after the abort signal has been sent
    htmTransactionStarts = 0;
    htmTransactionStops = 0;
}

BaseHTMCheckpointPtr&
SimpleThread::getHtmCheckpointPtr()
{
    return _htmCheckpoint;
}

void
SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
{
    _htmCheckpoint = std::move(new_cpt);
}

} // namespace gem5